Block Diagram -Cd Section - Sony CDX-M850MP Service Manual

CDX-M850MP
4-2. BLOCK DIAGRAM — CD SECTION —
OPTICAL PICK-UP
KSS-721A
B
A
84
D
C 85
A
B
82
C
I-V
D
83
CONV.
E
E
87
TRACKING
F
F 86
APC
PD
PD
97
LD
DRIVE
LD A+5V
Q1
LD
98
IC2
FOCUS/TRACKING COIL DRIVE,
SLED/SPINDLE/LOADING MOTOR DRIVE
FCS-
FOCUS
15
FOCUS
COIL
FCS+
COIL
16 DRIVE
TRK+
TRACKING
17
TRACKING
COIL
TRK-
COIL
18
DRIVE
SL-
M SLED
M902 13
MOTOR
(SLED)
SL+
14
DRIVE
SP+
SPINDLE
M 11
M901
MOTOR
(SPINDLE) SP-
12
DRIVE
LD-
LOADING
M
9
M903
MOTOR
(LOADING) LD+
10
DRIVE
IC1
RF AMP,DIGITAL SERVO
DIGITAL SIGNAL PROCESSOR
D/A
RF EFM CONV
EQ DEMOD
DSUB CODE
PROCESS
FORCUS
ERROR
I/F
ERROR
SERVO
CTL
OSC
62 63 64 65 23 24
X1
16.9344MHz
FD
26
TD
23
SD
5
MD
6
LOAD
1
EJECT
2
(Page 25)
TUNER
SECTION
LOUT
A
16
CDL
ROUT
12 R-CH
IC7
5V 3.3V
PACK
52
TSTB 3 17
56
TSCK
55
TSI
54
SI 14 6
8
SO
7
SCK
8
12
6
STB
5 15
5
AO
7
13
4
RST 9
11
3
RFOK
2
FLAG
28
XTALEN 16
4
9
C16M IC5
38
DSP
DIN 18 2
29
X1
62
DOUT
30
9 SDO
STANDBY
SCKIN
12 SDIO
31
SCKO
32 13 BCKIA
MIDIO(I2C_SDA)
LRCKIN
33
LRCK
34 14 LRCKIA
MICK(I2C_SCL)
IC4
S-RAM
46,47
DQ1-DQ3, 21-23
49-51 IO0-IO7
IO4-IO8 25-29
53-55
3,4
7,10
20-13
11,15
3,2,31
A0-A16 38-36 AD0-AD16
1,12,4
34-31
11,7,10
41,42
45,44
WR 5 43 WR
CS1 30 17 OE
OE 32 16 CE
IC6
+2.5V
+2.5V 3
REG
(IC5)
24 24
IC3
CD MASTER CONTROL
38 PACK
34 TSTB
83 TSO
84 TSI
85 TSCK
35 STB
36
AO
37 CD_RST
28 RFOK
27 FLAG
33 XTALEN
DECXRST
1 2
/RESET
19 3 DECSTBY
DECINT
REQ 39 72
5 80 SDA
IC12
1
4
6 81 SCL
2
63 XTAL
X2
12.288MHz
65 EXTAL
11 D_SW
SW5
(DOWN)
40 SELF SW
SW2
(SELF)
9 INSW/PH2
SW3
(DISC IN)
10 LIMIT_SW
2 BU+3.3V SW4
(LIMIT)
18 LOAD
17 EJECT
• R-ch is omitted due to
same as L-ch.
• Signal path
:CD
:CD-R/RW(MP3)
TUNER
SECTION
B
A-ATT
A-ATT 93
(Page 25)
SYSRST
RSTX 59
BU CHK
BUCHK 92
BUSON
DISPLY
BUSON 91
SECTION
BUS-CLK
UNI CK 78
C
BUS-SI
77
UNI_SI
(Page 26)
BUS-SO
UNI_SO 76
LINK-OFF
LINKOFF 75
CDMON
CDMON 71
DISPLY
CDON
SECTION
CDON 94
D
CLOSE
CLOSE 73
OPEN
OPEN 74
(Page 26)