Memory Subsystem; I/O Subsystem; System Bus; System Control - Fujitsu Sun Oracle SPARC Enterprise M3000 Overview Manual

2.1.2

Memory Subsystem

The memory subsystem controls memory access and cache memory. The M3000
server uses DDR2 SDRAMs and can contain up to eight memory modules. The
memory subsystem supports up to two-way memory interleaving for high-speed
memory access.
2.1.3

I/O Subsystem

The I/O subsystem controls data transfer with I/O devices.
The I/O subsystem of the M3000 server contains the following:
PCIe cards
■
PCIe (x8 lane) slots
I/O controller (IOC) chip, which is the bridge chip between the system bus and
■
the I/O bus
PCI Express switch connected to slots
■
SAS port
■
2.1.4

System Bus

The CPU, memory subsystem, and I/O subsystem are directly connected to
implement data transfer by using a high-speed broadband switch.
If a data error is detected in the CPU, memory access controller (MAC), or I/O
controller (IOC), the system bus agent corrects the data and then transfers it.
2.1.5

System Control

The M3000 server is controlled by the eXtended System Control Facility (XSCF). The
XSCF operates on a dedicated service processor, which operates independently from
the processor of the server. As long as the power is supplied to the server, the XSCF
constantly monitors the server even if the domain power is off.
For details, see
M3000/M4000/M5000/M8000/M9000 Servers XSCF User's Guide.
2-2 SPARC Enterprise M3000 Server Overview Guide • March 2012
Section 2.6, "XSCF Firmware" on page 2-7 and the SPARC Enterprise