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Sharp MZ-800 Service Manual page 22

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MZ-800
VRAM
to
CPU
interface
• As the CRTC bus is completely separated from the
CPU bus, read and write of the VRAM is carried out
through the CRTC. Therefore, interfacing with the
CPU is done via the read register or write register in
the CRTC.
• VRAM access by the CRTC is done under the pseudo
cycle steal mode.
• Not only read and write are for the accessing with
the CPU, it permits to read multiple number of screen
data logical operational results and to write the
read-modify-write of the logical operational results
for the data already written. So, it has two registers
of the read format register and the write format
register.
• It permits CPU access to the non-display plane in the
display mode according to the
BI
A bit and it enables
selection of data buffer and two screens, when the
32 KB VRAM is used.
a) Read format register (RF) (OUT
&
CD)
MSB
LSB
I
SR~I:G r~",r'''~] ~A
I
IV
!
III
11
*
NOTE: Same as the bit B/A of the write format register.
21
• SRCH/S I NG
"0": Single color data read .....
Reads the data of the color plane, 1,
IT,
rn,
or N,
specified by "1 ".
NOTE:
Only one item should be "1" out of
I, IT,
rn,
and
N.
If it is "1" for more than two or
non-existence of the VRAM
may not
assure the data read.
"1": Specified color search .....
"1" is retu rned for the bit of the color specified by
0/1
of
I, IT,
rn,
and
N.
NOTE:
Depending on the display more, color
combination is permitted for the bit com-
bination of
L IT, ID, N; ID, N; I, IT; I;
and
ID.
Bit combination otherwise will be dis-
regarded.
• B/A
(ex. For the 640 x 200, 4-color mode,
combination becomes possible for I and
ID,
and
IT
and N are disregarded.
CPU access plane change
MZ-800
--->
"0": Frame A access .....
Accesses the frame A (planes I and
IT
for the 320
x 200, 4-color mode; plane I for the 640 x 200,
1-color mode).
"1": Frame B access .....
Accesses the (planes
ID
and N for the 320 x 200,
4-color mode; plane
IT
for the 640 x 200, 1-color
mode).
• L
IT, ID,
N ..... Color plane designation.
I
f
I
!

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