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Sharp MZ-800 Service Manual page 20

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MZ-800
800 MODE (640
X
200 dot)
DISP. cycle
-I·
CPU cycle
-I·
DISP. cycle
VRAS
,'---___
----~I
\~--
__
----_~I
\ ' - - - - -
VCAS
\'---~/
''---~
\~-----------~
\'-----
VOE
,'-------/
,
VAD 0 - 7
~
ROW
X' _ _ __
CO_L_.
----' X ' _ _ __
C_O_L._~'C~'__
_ _ _ _ _ _
_:_--~X
X' - __ --,--_
'---;;~
N+1th adr.
'------C~
~===N=+=-2th~ad-r.~~
VA 0 - 7
-------~~~----~~~----~<==>~------------------~
I plane N th DATA
I plane N+l th DATA
cPU read DATA
vc
0 - 7
----------~~~----~~~----~<==>~---------------~
III plane Nth DATA
1II
plane N+ 1th DATA
CPU read DATA
LOAD
(sift register)
LJ
CPU and VRAM accessing
1. Accessing of the VRAM by the CPU is carried out in
the cycle steal mode (MZ-800 mode only) during the
flyback period of the display under the control of the
CRT controller.
2. Even when there is no accessing from the CPU in the
CPU cycle, such as VRAS, VCAS, VOE, etc. are
outputted in the timing of the read cycle at all times.
3. Write to the VRAM is carried out after logical opera-
tion of the read and write data by means of the
read-modify-write method. But, in the case of the 320
x 200, 16-color mode, data are written in two CPU
cycles as there is a need of writing to Plane IV.
See separate paper for timing chart.
4. CPU wait
1) Write
• As there is a one-byte buffer in the CRT controller,
write to the VRAM from the CPU is carried out
through the buffer. But, actual write to the VRAM is
cpu cycle
<D
done by the CRT controller. Therefore, there would
be no need of wait under almost any condition in the
MZ-800 mode.
• Even in the MZ-700 mode, wait is issued when there
are more than two writes in a display period.
Display period
Flyback period
HBLN
~r-.-----------1.l"
' - - _____ _
~:~~w:R-----LJ~<D~-----t-L----~®l--,~rl-,-:------
~t..._J
<D@
WAIT
------------4,,\
".)r.
) l " - - - - -
'- _ _ _ _ _ _ J
2) Read
Wait is issued along with the CPU write action both
during displaying and flyback periods to perform
reading operation in synchronization with the CPU
cycle.
DISP. cycle
cpu cycle@
~-
-I-
. . - - - - - - . - - - - - - - -
- _ . r - ' I
.~
- - - - - - - - - - - -
VRAS
-.J
\
\
r
VCAS
~
\
\~-----------
V OE
~
\
VADO-7
~
ROW
X
COL.
~~~======~----x'--~~==x~====~x===~~~x
ROW
X' - -__
C_O_L. _ _ _ _ _ _ _ _ _
X
CPU adr. latch DATA I. III plane
DISP. adr.
11.
IV
plane
VRWR
L-.J
VA
0-7
----~CJ:J___{
I plane
)>--------<c=::)>-----c=>-~
read DATA
write DATA
VC
0,-7
-----~
1II
plane
)>---------<c=::)>-----c=>>-----QD---(
IV
plane } - -
19
DISP. DATA

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