I
MZ-800
Pin conflgur.tlon
GNO
ADO
AOl
AD'
AD7
...
AOO
AOA
ADO
ADC
AOO
AD'
OTO
on
072
073
0"
0"
on
on
GNO
TlM'
m
~G
JOY
IIOIIT
IIISTO
CI"$
IOWR
TEST
KEY
C&3
CKMS
CIJR
MOO
MNIfT
SIC
lORD
MOO'
Mm
CJIIOM
""IIJ
lO!SH
lilT
~
VI[R
VJIA!"
VADO
VA02
VA04
VAD6
WJr
~
SEll
[NHS
GND
~
VAD'
VADJ
VAOS
VA07
GNO
.....
......
~TN
G"N
BlUE
•• 0
sac.
VC>
VCI
vet;
\IC4
VC,
VC2
VC.
\/CO
VA7
VAB
VAS
VM
VA3
VA2
VA1
VAD
.....
GNO
Custom LSI block diagram
VSYN
SBCR
HSYN
VBlN
CKMS
CPU
CLKO
NTPL
ADO - F
DTO -7
RD
WR
MREO
M1
10RO
RFSH
CROM
SEL1
CASB
INHS
CPR
KEY
C53
53G
JOY
PSG
CRS
SIO
lORD
10WR
WTGD
,16
8
I
Clock generator
&
timing generator
CPU address
CPU
CPU
VF
CONTROL
t - -
Memory
I--
controller
----
110
controller
WAIT
controller
•
--1
Display address
generator
-
~
DATA
I
)~
MPX
I
R~iSplay contro
T
.--
register
+
~
Rscroll
register~
I--
Scroll circuit
!
t
~
MPX
l
VRAM address
controller
!
r
MPX
l
1
VRAM
1
-I
Timing control
1
VRAS
11
8
VCAS
VRWR VADO-7
VROE
Vcc
2, 29, 52, 79,
pin
GND 3, 28, 40, 53, 78 pin
PORT MNRT
RESET
I
-
Input
BUFF
-
Pallet
circuit
Shift
register
~
VRAM data
110
circuit
, 8
8
VAO-7
VCO-7
RSTO
MOD7
TEMP
RED
GREN
BLUE
YITN
1·