For plane read data from the VRAM, data to be read
by the CPU are arranged in accordance with the
direction of the read format register (RF).
Read data from the VRAM and write data from the
CPU are subjected to logical operation (OR, XOR,
RESET, etc.) and its result is used for the write data.
VRAM acee .. timing
1) MZ-700 mode
See separate page for display timing chart.
The VRAM is configured in the following manner in
As the PCG method is adopted for the MZ-700 mode,
the text and ATB areas are actually mapped to $0000
- $OFFF. So, the VRAM address has the following
relation with the display character position.
2) MZ-800 mode
As the bit map method is used for the MZ-800 mode,
it is possible to four screens of 320 x 200 dots and
two screens (maximum) of 640'x 200 data.
The cycle steal method is used for this mode.
i) 320 x 200 dots
See separate page for the timing chart duing
display and CPU read timing.
What i. p.eudo cycle steal
With the MZ-800, the pseudo cycle steal method is
adopted for VRAM accessing.
OISP. addr .. s
OISP. add re ..
As shown in the figure, a next display data fetch and
CPU accessing are multiplexed during a display period.
Because accessing of the VRAM while characters are on
display causes the screen to blink with the MZ-700
mode, it awaits for blinking to complete before acces-
sing of the VRAM. But, with the cycle steal method it
enhances faster screen processing as it enables to
access the VRAM during a display period. Because it is
not a complete cycle steal with the MZ-800 but timing is
taken using a wait in order to synchronize with the CPU
cycle for accessing from the CPU, it is therefore called
"pseudo cycle steal