Z80-CPU Data Bus
Bidirectional, 3-state, Z-80 CPU bus.
Data and command transfer between the Z-80 CPU and the
PlO is carried out through this data bus. Do is the least
Port B or A Select
Port select signal.
Depending on the state of this signal, the port is specified
through which data or command is transferred between the
Z-80 CPU and the PlO.
}H : Port B
L : Port A
Control or Date Select
Controlldata select signal.
Depending on the state of this signal, control port or data
port is selected for the port assigned with B/A.
Port A data
Port A control
Port B data
Port B control
Chip enable signal.
A low on this line enables the PlO. Normally connected with
address decoder output.
CPU clock 1/1 is usually used.
Machine Cycle One
Connection with CPU M1 signal (Iow active).
The PlO attains synchronization with the CPU interrupt
control logic by M1. The PlO will be reset when M1 is set
low at least for a period of two clock cycles after turning
Input Output Request
Connection with CPU iORQ signal (Iow active).
This signal perform data transfer between the CPU and the
PlO in connection with B/A,
and RD. If
iORQ are low, the data on the port selected by B/A are
transferred to the CPU. If
iORQ are low, data or
command is written through the port selected by B/A.
Connection with CPU RD signal (Iow active).
This signal controls the direction of data transfer between
the CPU and the PlO in connection with B/A,
Interrupt Enable in
Interrupt daisy chain signal. The PlO will respond to the
INTA cycle of the CPU only when this signal is high.
Interrupt Enable Out
Interrupt daisy chain signal. This signal is high only when
IEI is not high with the PlO having an interrupt request. It
goes low when IEI is low or PlO is having an interrupt