Sharp LC-42XL2S Service Manual page 154

LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
Ref No.
—
AL29, V29, C30
AL30, V30, D30
AK29
OTHER
C26
AJ7
K3
K2
AM6
AL6
AK6
2.17. IC8301-4 (RH-iXC154WJQZQ)
2.17.1 Pin Connections and short description
Pin No. Pin Name
53, 52 CK, CK
41 CKE
51 CS
19 ODT
77, 76, 70 RAS, CAS, WE
66, 62 (L) UDM
42, 71 BA0 - BA1
50, 72, 75, A0 - A12
44, 49, 73,
74, 45, 48,
46, 43, 47, 13
DQ
81, 57, LDQS, (LDQS)
61, 29 UDQS, (UDQS)
10, 14, 15, NC/RFU
16, 32, 36,
3, 7, 22, 24, VDDQ
26, 28, 63,
67, 80, 84
Pin Name I/O
VSS — IO ground related to VDDF./Core ground related to VDDC.
A31, A34, AA6, AA14, AA15, AA16, AA17, AA18, AA19, AA20, AA21, AB6, AB15,
AB16, AB17, AB18, AB19, AB20, AB31, AB34, AC6, AC29, AC32, AD31, AF29,
AF32, AG31, AG34, AH32, AJ13, AJ14, AJ15, AJ21, AJ23, AJ24, AJ25, AJ26, AJ31,
AJ34, AK32, AL31, AN16, AN23, AN29, AN32, AP31, AP34, B32, D31, E29, E32,
F10, F11, F12, F13, F14, F15, F20, F21, F22, F31, F34, G32, H31, H34, J29, J32,
K31, M29, M32, N6, N15, N16, N17, N18, N19, N20, N31, N34, P6, P14, P15, P16,
P17, P18, P19, P20, P21, P29, P32, R6, R13, R14, R15, R16, R17, R18, R19, R20,
R21, R22, R31, R34, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22, T29, T32,
U13, U14, U15, U16, U17, U18, U19, U20, U21, U22, U31, V13, V14, V15, V16, V17,
V18, V19, V20, V21, V22, V33, W13, W14, W15, W16, W17, W18, W19, W20, W21,
W22, W32, Y13, Y14, Y15, Y16, Y17, Y18, Y19, Y20, Y21, Y22, Y31, Y34
MVREF — Memory interface voltage reference.
VDDR — 1.8V input buffer reference power.
VSSR — Ground of input buffer reference power.
RESET# I System reset input, high active.
FULL_EJTAG I 1: Full EJTAG, 0:simple EJTAG.
VCOTP O DEMUX output.
CLK27M I DEMUX input.
PCMOD I 1: PC MODE (Not used)
TESTCON I Test mode control.
TESTMOD I Test mode input.
I/O
I Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the
positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK
and CK (both directions of crossing).
I Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input
buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh opera-
tion (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power
down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be
maintained high throughout read and write accesses. Input buffers, excluding CK, and CKE are disabled
during powerdown. Input buffers, excluding CKE, are disabled during self refresh.
I Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank
selection on systems with multiple banks. CS is considered part of the command code.
I On Die Termination: ODT (registered HIGH) enables termination resistance internal to the gDDR2
SDRAM. When enabled, ODT is only applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM
signal for x16 configurations. The ODT pin will be ignored if the Extended Mode Register (EMRS) is pro-
grammed to disable ODT.
I Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
I Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled
HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
I Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge com-
mand is being applied. BA0 also determines if the mode register or extended mode register is to be
accessed during a MRS or EMRS cycle.
I Address Inputs: Provided the row address for Active commands and the column address and Auto Pre-
charge bit for Read/Write commands to select one location out of the memory array in the respective
bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one
bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by
BA0, BA1. The address inputs also provide the op-code during Mode Register Set commands.
I/O Data Input/ Output: Bi-directional data bus.
I/O Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write
data. LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15.
The data strobes LDQS and UDQS may be used in single ended mode or paired with optional comple-
mentary signals LDQSand UDQS to provide differential pair signaling to the system during both reads
and writes. An EMRS (1) control bit enables or disables all complementary data strobe signals.
— No Connect: No internal electrical connection is present.
DQ Power Supply: 1.8V ± 0.1V.
—
Pin Function
Pin Function
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