HP 9000 Series 310 Service Information Manual page 54

9000 series 300 computers and bus expander
Table of Contents

Advertisement

Address Decode/
Milc. Signals
i}
=
-illl; -
'/0 C.o',., B", - .-o''"-+--
-+---t-------<t----+-_+_
CtI,p (ngble BUI
F"mDI';:'~mBI"k~"" ~i
-
VD
C1OO".
B"
-r-'-----'----1
TI
CUltom
10 IroIH'Z>------------
-
-
Chip
2
External
I/O Registers/
Interrupt/Mise
Signals
From CPU Blgel(
010 OcJtg
~
_________ _
~
~,@-o~
DIClQrgm
g~
To 010
Addre ..
Buff.r.
I/o
Control
Signal
I
010
Control
au.
/1'
010 Control
I
Signals
I/O Interrupt.
010 Interrupt
line.
/
/
"
~
-
..
~
~~
Logical Addr ...
.!.3
0
£
i
Control
(.)
~
'-r-
010
Addr... Bu.
l'
1
I
1
TLB RAM
II
J
I
lower 010
1
Upper Address
Address
II
i
I
OlD ...
".~
Lot"/Bu""
~
1
Buffer Control_1
J
.----
t.1MU/ORAM
II
Controller
II
~
r!
(MCA2BOOALS
Phy.Jcal Addre.. Bus
~~
Gate Array)
:::J
!ID
.----
e
RAM
Control
~
~r!
8~
- -
:::J
Buffered
RAM
Contro~_
!ID
To
I/O
Data
Buffer.
I
010 Data
Buffers
~
010
o.t.
au.
I
~
Procellor Doto Bu. (olio RAM Parity)
I
I
Test Conector
I
Buffer Controt
,,1/
10 101HZ
Figure 3-4. 98561-66511 Processor Board Block Diagram
44 Functional Description
1/2 MEG
RAM Array
With Pority
I

Advertisement

Table of Contents
loading

This manual is also suitable for:

98568a

Table of Contents