System Timer; Central Processing Unit; Ram - HP 9000 Series 310 Service Information Manual

9000 series 300 computers and bus expander
Table of Contents

Advertisement

System Timer
With the variety of processor boards and the difference in instruction execution speeds between
many of these
boards~
Series 200 software required hardware support for its time dependent
operations. The MC6840 timer is the device this processor board uses.
There are no external registers implemented to supplement the registers which already exist
within the MC6840. Registers within the MC6840 are multiple-mapped within a 16 K-byte
menlory region.
For information as to the functioning of the registers within the MC6840, refer to the MC6840
Programmable Timer Module (PTM) data sheet which can be found in the Motorola Micropro-
cessors Data Manual.
Central Processing Unit
A lVlotorola MC68010 CPU functions as the main processor chip on this assembly. Operating
at 10 MHz, it provides fast instruction time.
Its asynchronous data bus is 16-bits wide for both addresses and internal registers. The MC68020
CPU can address 16 M-bytes of RAM and can directly address 7.5 M-byte of RAM. Operating
at 10 MHz, it is somewhat slower than the
~C68020
CPU.
The CPU has 57 instruction types and handles 5 major data types. It also has 14 addressing
modes, 6 maskable and 1 non-maskable interrupt levels.
RAM
One-half M-byte of RAM is installed on the 98561-66511 board. This RAM has optional parity
and is auto-locating to 0.5 M-byte boundaries in the computer's memory map. Auto-locating
means the processor's RAM will respond to 0.5 M addresses that exists immediately below blocks
of addresses the accessory RAM cards are configured for. This block of addresses may also be
between the address accessory RAM cards are configured for providing exactly 0.5 M addresses
exist. If accessory RAM cards are configured such to have an empty section of RAM of less
than or greater than 0.5 M addresses, an error will occur during the turn-on memory test. RAM
control is performed by an MCA2800ALS gate array which also serves as the MMU.
Optional RAM cards installed in accessory slots have access times somewhat slower than RAM
on the processor board. RAM cards in the I/O card cage has a minimum access time of approx-
imately 620 nano-seconds compared to the 400 nano-second access time for processor on-board
RAM.
Functional Description 45

Advertisement

Table of Contents
loading

This manual is also suitable for:

98568a

Table of Contents