TMC AI5VG+ User Manual page 52

Chapter 6 BIOS Configuration
IRQ3/4/5/7/9/10/11/12/14/15, DMA0/1/3/5/6/7 assigned to
These fields allow you to determine the IRQ/DMA assigned to the ISA
bus and is not available to any PCI slot.
CPU to PCI Write Buffer
When enabled, this option increase the efficiency of the PCI bus to and
speed up the execution in the processor. By default, this field is set to
Enabled.
PCI Dynamic Bursting
When enabled, this option combines several PCI cycles into one. By
default, this field is set to Enabled.
PCI Master 0 WS Write
When enabled, this option increases the write cycle speed. By default,
this field is set to Enabled.
PCI Delay Transaction
When enabled, this option delays PCI data transaction. By default, this
field is set to Enabled.
PCI Master Read Prefetch
When this item is enabled, the system is allowed to prefetch the next read
and initiate the next process. By default, this field is set to Enabled.
PCI#2 Access #1 Retry
This item enables PC#2 Access #1 attempts. By default, this field is set to
Disabled.
AGP Master 1 WS Write
When enabled, writes to the AGP bus are executed with 1 wait states. By
default, this field is set to Enabled.
AGP Master 1 WS Read
When enabled, reads to the AGP bus are executed with 1 wait states. By
default, this field is set to Disabled.
PCI IRQ Activated by
This field allows you to select the method by which the PCI bus
recognizes that an IRQ service is being requested by a device. The
default value is Level.
48 AI5VG+ User's Manual