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P2-0
P2-1
PROGRAMMABLE
P2-2
DMA
P2-3
CONTROLLER
P2-4
P2-5
TxD0
RxD0
SERIAL
P1-6
COMMUNICATION
CTS0
INTERFACE
TxD1
RxD1
BAUD RATE
CTS1
GENERATOR
P1-0
P1-1
PROGRAMMABLE
P1-2
INTERRUPT
P1-3
CONTROLLER
P1-4
X1
CLOCK
X2
16-BIT TIMER
P1-5
Manual reset can be accomplished by pressing
push-button switch S1. When U17, pin 2 goes low,
U17 goes into the reset sequence described.
6.11.3 HIGH SPEED DATA BUS MICROPRO-
CESSOR (U13)
The HSDB processor (U13) on the MPC pro-
vides the interface with the HSDB. It monitors data
on this bus and also transmits data on to this bus when
necessary. Information on this bus indicates which
repeaters are in use and also which mobiles are using
the system. This information is used by the repeater to
encode data messages to the mobiles that are monitor-
ing that channel. These messages also include infor-
mation on which repeater is free and current system
priority.
LC
etc.
PSW
PC
INSTRUCTION DECODER
TIME BASE CONTROLLER
REFRQ
P0-7
P0
Figure 6-15 U27 BLOCK DIAGRAM
STAGING
LATCH
ALU
TA
TB
TC
INT RAM
256 BYTES
GR
MACRO
SERVICE
CHANNEL
MICRO SEQUENCER
MICRO ROM
QUEUE
PORT WITH
PORT
COMPARATOR
V
P1
P2
PT0-PT7
Microprocessor U13 is an 8052 that uses external
EPROM (Erasable Programmable Read Only Mem-
ory) U14, an 8-bit device that stores the program. The
microprocessor uses 2k x 8 EPROM and 64k x 8
RAM. The RAM (Random Access Memory) is used
for temporary data storage. The HSDB processor is
configured by the Main Processor.
The internal data bus of the microprocessor has
four input/output ports. These ports have eight lines
each, giving a total of 32 input/output lines. These
ports are designated P0, P1, P2, P3. P0 is used as a
data bus. Ports P1 and P2 are always used as general
purpose inputs/outputs. P3 is used for specialized
functions, i.e. a serial port (RxD/TxD) and interrupt
(INT).
6-35
CIRCUIT DESCRIPTION
STAGING
ADM
LATCH
PFP
INC
RESET
INT ROM
P2-6
16K BYTES
P2-7
P1-7
MSTB
MREQ
R/W
IOSTB
EA
P1-4
TH
Part No. 001-2009-201
A19-A0
D7-D0
October 1999
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