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Summary of Contents for Supero X5DL8-GG
- Page 1 ® UPER SUPER X5DL8-GG SUPER X5DLR-8G2+ SUPER X5DLR-8G2 USER’S MANUAL Revision 1.0a...
- Page 2 The information in this User’s Manual has been carefully reviewed and is believed to be accurate. The vendor assumes no responsibility for any inaccuracies that may be contained in this document, makes no commitment to update or to keep current the information in this manual, or to notify any person or organization of the updates.
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Page 3: Preface
About This Manual This manual is written for system integrators, PC technicians and knowledgeable PC users. It provides information for the installation and use of the SUPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 serverboard. At launch, the SUPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 supported single or dual ® Intel Xeon 1.50 - 2.80 GHz processors at a 533/400 MHz front side bus. -
Page 4: Table Of Contents
Contacting Supermicro ................1-2 Super X5DL8-GG Image ................. 1-4 Super X5DLR-8G2 Image ................ 1-5 Super X5DL8-GG Layout ................ 1-6 Super X5DL8-GG Quick Reference ............1-7 Super X5DLR-8G2 Layout ..............1-8 Super X5DLR-8G2/X5DLR-8G2+ Quick Reference ......1-9 Motherboard Features ................1-10 ServerWorks GC - LE Chipset System Block Diagram .... - Page 5 Speaker Enable/Disable ..............2-16,17 Fan Detection Select ................2-17 Chassis/Overheat Fan Select ............... 2-17 Watch Dog ....................2-17 GLAN1 Enable/Disable ................2-18 GLAN2 Enable/Disable ................2-18 SCSI Enable/Disable ................2-18 SCSI Termination Enable/Disable ............2-18 PCI-X Bus Speed Setting (X5DL8-GG) ..........2-19...
- Page 6 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual PCI-X Bus Speed Setting (X5DLR-8G2/X5DLR-8G2+) ...... 2-19 33 MHz PCI Enable/Disable ..............2-19 Front Side Bus Speed ................2-20 Spread Spectrum ..................2-20 PCI 3.3V Standby Enable/Disable ............2-20 VGA Enable/Disable ................2-20 Main Power Override ................2-21 Parallel Port, Floppy/Hard Disk Drive and SCSI Connections ....
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Page 7: Chapter 1: Introduction
Chapter 1: Introduction Chapter 1 Introduction Overview Checklist Congratulations on purchasing your computer motherboard from an ac- knowledged leader in the industry. Supermicro boards are designed with the utmost attention to detail to provide you with the highest standards in quality and performance. -
Page 8: Contacting Supermicro
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Contacting Supermicro Headquarters Address: SuperMicro Computer, Inc. 980 Rock Ave. San Jose, CA 95131 U.S.A. Tel: +1 (408) 503-8000 Fax: +1 (408) 503-8008 Email: marketing@supermicro.com (General Information) support@supermicro.com (Technical Support) Web Site: www.supermicro.com Europe Address: SuperMicro Computer B.V. - Page 9 Chapter 1: Introduction Notes...
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Page 10: Super X5Dl8-Gg Image
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Figure 1-1. SUPER X5DL8-GG Image... -
Page 11: Super X5Dlr-8G2 Image
Chapter 1: Introduction Figure 1-2. SUPER X5DLR-8G2 Image Note: the X5DLR-8G2+ has the same layout but has 1) no parallel (printer) port and 2) a standard PCI-X slot. -
Page 12: Super X5Dl8-Gg Layout
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Figure 1-3. SUPER X5DL8-GG Layout (not drawn to scale) JP48 Keyboard/Mouse ATX POWER Bank 1A OH/CHS FAN USB0/1 Bank 1B CPU1/CHS FAN Bank 2A CPU1 Bank 2B COM1 Bank 3A Parallel Bank 3B Port ® UPER... - Page 13 Chapter 1: Introduction X5DL8-GG Quick Reference Jumper Description Default Setting 33 MHz PCI Enable/Disable Open (Disabled) Spread Spectrum Open (Disabled) SCSI Enable/Disable Pins 1-2 (Enabled) JBT1 CMOS Clear See Chapter 2 PCI 3.3V Standby En/Dis Pins 1-2 (Disabled) Watch Dog...
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Page 14: Super X5Dlr-8G2 Layout
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Figure 1-4. SUPER X5DLR-8G2 Layout* (not drawn to scale) Keyboard/Mouse ATX POWER JP46 Bank 2B OH/CHS FAN USB0/1 Bank 2A JP48 Bank 1B CPU1 Bank 1A COM1 CPU1/CHS FAN Bank 0B Parallel Bank 0A JP12 Port ®... - Page 15 Chapter 1: Introduction X5DLR-8G2+/X5DLR-8G2 Quick Reference Jumper Description Default Setting Spread Spectrum Open (Disabled) SCSI Enable/Disable Pins 1-2 (Enabled) JBT1 CMOS Clear See Chapter 2 Speaker Enable/Disable Closed (Enabled) Watch Dog Pins 2-3 (NMI) JP12 System Bus Speed Pins 1-2 (Auto) JP48 Chassis/Overheat Fan Select Open (Overheat)
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Page 16: Motherboard Features
Note: Please refer to the motherboard specifications pages on our web site for updates on supported processors (http://www.supermicro.com/Product_page/product-m.htm). M e m o r y • X5DL8-GG: Eight 184-pin DIMM sockets supporting up to 16 GB of registered ECC DDR-266/200 (PC2100/1600) SDRAM • X5DLR-8G2+/X5DLR-8G2: Six 184-pin DIMM sockets supporting up to 12 GB of registered ECC DDR-266/200 (PC2100/1600) SDRAM Note: Memory is 2-way interleaved meaning DIMM modules must be installed two at a time. - Page 17 • Adaptec 2015S SCSI RAID support (X5DLR-8G2+/X5DLR-8G2) • Integrated ATI Rage XL Graphics Controller • Intel 82540EM Gb Ethernet controller (X5DL8-GG - LAN1) • Broadcom BCM5703 Gb Ethernet controller (X5DL8-GG - LAN2) • Broadcom BCM5704 dual Gb Ethernet controller (X5DLR-8G2+/X5DLR- 8G2) •...
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Page 18: System Block Diagram
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual PCI-X Slots #4, 5 ATI XL Processor 1 Processor 0 PCI Bus ATA 100 533/400 MHz Host Bus Thin IMB Ports CSB5 North Bridge IMB BUS CIOBX2 (South LAN2 (IO Bridge) (CMIC-WS) Ports Bridge) PCI-X Slot #6... -
Page 19: Chipset Overview
SMBus. The CIOBX2 is an integrated IO bridge that provides high-performance data flow between the IMB interface and the dual peer PCI-X bus interfaces. The X5DL8-GG has two CIOBX2 bridges (four buses). Special Features ATI Graphics Controller The X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 has an integrated ATI video con- troller based on the Rage XL graphics chip. -
Page 20: Pc Health Monitoring
Always On. PC Health Monitoring This section describes the PC health monitoring features of the SUPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2. It has an onboard System Hardware Monitor chip that supports PC health monitoring. Onboard Voltage Monitors for the CPU Cores, Chipset Voltage, +5V, +12V and 5V Standby An onboard voltage monitor will scan these voltages continuously. -
Page 21: 1-5 Acpi Features
Chapter 1: Introduction System Resource Alert This feature is available when used with Intel's LANDesk Client Manager (optional). LDCM is used to notify the user of certain system events. For example, if the system is running low on virtual memory and there is insuf- ficient hard drive space for saving the data, you can be alerted of the potential problem. - Page 22 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Microsoft OnNow The OnNow design initiative is a comprehensive, system-wide approach to system and device power control. OnNow is a term for a PC that is always on but appears to be off and responds immediately to user or other re- quests.
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Page 23: Power Supply
As with all computer products, a stable power source is necessary for proper and reliable operation. It is even more important for processors that have high CPU clock rates. The SUPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 accommodates ATX power supplies. Although most power supplies generally meet the specifications required by the CPU, some are inadequate. - Page 24 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual complete modem control capability and a processor interrupt system. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability and a processor inter- rupt system. Both UARTs provide legacy speed with baud rate of up to 115.2 Kbps as well as an advanced speed with baud rates of 250 K, 500 K,...
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Page 25: Chapter 2: Installation
Chapter 2: Installation Chapter 2 Installation Static-Sensitive Devices Electric-Static-Discharge (ESD) can damage electronic components. To pre- vent damage to your system board, it is important to handle it very carefully. The following measures are generally sufficient to protect your equipment from ESD. -
Page 26: Pga Processor And Heatsink Installation
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual PGA Processor and Heatsink Installation When handling the processor package, avoid placing direct pressure on the label area of the fan. Also, do not place the motherboard on a conductive surface, which can damage the BIOS battery and prevent the system from booting up. - Page 27 Chapter 2: Installation 4. Secure the other retention bracket into position by repeating Step 3. 5. Lift the lever on the CPU socket: lift the the lever completely or you Socket lever will damage the CPU socket when power is applied . (Install CPU1 first.) 6.
- Page 28 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Figure 2-1. PGA604 Socket: Empty and with Processor Installed Empty socket Lever Warning! Make sure you lift the lever completely Triangle when installing the CPU. If the lever is only partly raised, damage to the Processor...
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Page 29: Installing Dimms
DIMM Installation (See Figure 2-2) 1. Insert an even number of memory modules. Interleaved memory requires you to install two modules at a time. With the X5DL8-GG, begin from the two slots of the last bank and working your way toward the two slots of Bank 1. -
Page 30: Ioports/Control Panel Connectors
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Figure 2-2. Installing and Removing DIMMs To Install: Insert the module vertically and press down until it snaps into place. Pay attention to the notch on the bottom of the module. To Remove: Use your thumbs to... -
Page 31: Front Control Panel
Chapter 2: Installation Front Control Panel JF1 contains header pins for various front control panel connectors. These connectors are designed for use with Supermicro server chassis. Figure 2-4 for the pin locations of the various front control panel buttons and LED indicators. Refer to the following section for descriptions and pin definitions. -
Page 32: Connecting Cables
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Connecting Cables AT X Power Supply 24-pin Connector ATX Power Connector Pin Definitio ns Pin Number Definition Pin Number Definition +3.3V +3.3V power supply connector -12V +3.3V meets the SSI (Superset ATX) 24- PS_ON# pin specification, however it also supports a 20-pin power supply connector. -
Page 33: Hdd Led
Chapter 2: Installation HDD LED (ID E ) H D D L E D P in D e fin itio n s The HDD LED (for IDE and SCSI (J F 1 ) disk drives) connection is located P in N umb er D efinition on pins 13 and 14 of JF1. -
Page 34: Power Fail Led
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Power Fail LED P o w e r F a il L E D P in D e fin itio n s (J F 1 ) The Power Fail LED connection is P in located on pins 5 and 6 of JF1. -
Page 35: Serial Ports
Chapter 2: Installation Serial Ports S e ria l P o rt P in D e fin itio n s (C O M 1 , C O M 2 ) The COM1 serial port is located P in N um ber D efinition P in N um ber D efinition... -
Page 36: Hd Led Indicator
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual HD LED Indicator (JF2) The HD LED connector located at JF2 is used to indicate activity on any hard drive (IDE, SCSI or CD- ROM). Power LED (JF2) The Power LED connection located at JF2 is used to inform you that power is being supplied to the motherboard. -
Page 37: Wake-On-Lan
Chapter 2: Installation Wake-On-LAN (X5DL8-GG) W a k e -O n -L A N P in D e fin itio n s (W O L ) The Wake-On-LAN header is des- P in N umber D efinition ignated as WOL. See the table on... -
Page 38: Onboard Indicators
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Onboard Indicators GLAN1/GLAN2 LEDs Each of the Ethernet ports (located beside the VGA port) has a yellow and a green LED. See the tables below for the functions associated with these LEDs. On each Gb LAN port, the yellow LED indicates activity while the other LED may be green, orange or off to indicate the speed of the connec- tion (as specified in the tables below). -
Page 39: Cr5 Led
Chapter 2: Installation CR5 LED O n b o a rd L E D P o w e r In d ic a to r (C R 5) CR5 is an onboard LED that serves LE D C olor D efinition as a power indicator. -
Page 40: Jumper Settings
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Jumper Settings Explanation of Jumpers C o n n e c t o r Pins To modify the operation of the motherboard, jumpers can be used choose between J u m p e r C a p optional settings. -
Page 41: Fan Detection Select
Chapter 2: Installation SpeakerEnable/Disable (X5DLR-8G2+, X5DLR-8G2) S p e a k e r E n a b le /D is a b le J u m p e r S e tting s (J P 2 ) To disable the onboard speaker, Jumper P osition D efinition... -
Page 42: Glan1 Enable/Disable
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual GLAN1 Enable/Disable L A N 1 (X5DL8-GG) E n a b le /D is a b le J u m p e r S e tting s (J P 5 4 ) Change the setting of jumper JP54... -
Page 43: Pci-X Bus Speed Setting (X5Dl8-Gg)
Chapter 2: Installation PCI-X Bus Speed Setting (X5DL8-GG) P C I-X S lo t B u s S p e e d S e ttin g s P in D e fin itio n s (P 1 , P 2 , S 1 , S 2 ) -
Page 44: Front Side Bus Speed
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Front Side Bus Speed F ro n t S id e B us S p e e d J u m p e r S e tting s (J P 1 2 ) JP12 is used to set the system... -
Page 45: Main Power Override
Chapter 2: Installation Main Power Override (X5DL8-GG) P o w e r O n J u m p e r S e tting s (J P 1 ) Instead of using the chassis Jumper power on switch, you may close... -
Page 46: Floppy Connector
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Floppy Connector The floppy connector is located on J12. See the table below for pin definitions. F lo p p y C o n n e c to r P in D e fin itio n s (J P 1 2 ) -
Page 47: Ultra320 Scsi Connector
Chapter 2: Installation Ultra320 SCSI Connector Refer to the table below for the pin definitions of the Ul- tra320 SCSI connectors lo- cated at JA1 and JA2. 6 8 -p in U ltra 3 2 0 S C S I C o n n e c to rs (J A 1 a n d J A 2 ) C onnecto r C onnecto r C ontact... -
Page 48: 2-10 Installing Software Drivers
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual 2-10 Installing Software Drivers After all the hardware has been installed you must install the software drivers. The necessary drivers are all included on the Supermicro CD that came packaged with your motherboard. After inserting this CD into your CDROM drive, the display shown in Figure 2-5 should appear. -
Page 49: Chapter 3: Troubleshooting
Chapter 3: Troubleshooting Chapter 3 Troubleshooting Troubleshooting Procedures Use the following procedures to troubleshoot your system. If you have followed all of the procedures below and still need assistance, refer to the ‘Technical Support Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter. -
Page 50: Memory Errors
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual NOTE If you are a system integrator, VAR or OEM, a POST diagnos- tics card is recommended. For I/O port 80h codes, refer to App. B. Memory Errors 1. Make sure the DIMM modules are properly and fully installed. -
Page 51: Frequently Asked Questions
Question: What are the various types of memory that the X5DL8- GG/X5DLR-8G2+/X5DLR-8G2 motherboard can support? Answer: The X5DL8-GG has eight and the X5DLR-8G2+/X5DLR-8G2 has six 184-pin DIMM slots, which support registered ECC DDR-266 and DDR- 200 (PC2100 and PC1600) DIMMs only. - Page 52 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual find the readme.txt (flash instructions), the flash.bat (BIOS flash utility) and the BIOS image (xxxxxx.rom) files. Copy these files onto a bootable floppy and reboot your system. It is not necessary to set BIOS boot block protec- tion jumpers on the motherboard.
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Page 53: Returning Merchandise For Service
Chapter 3: Troubleshooting BIOS is not in control such as during memory count (the first screen that appears when the system is turned on), the momentary on/off switch must be held for more than four seconds to shut down the system. This feature is required to implement the ACPI features on the motherboard. - Page 54 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Notes...
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Page 55: Chapter 4: Amibios
Chapter 4 AMIBIOS Introduction This chapter describes the AMIBIOS for the X5DL8-GG/X5DLR-8G2+/X5DLR- 8G2. The AMI ROM BIOS is stored in a Flash EEPROM and can be easily upgraded using a floppy disk-based program. Note: Due to periodic changes to BIOS, some settings may have been added or deleted and might not yet be recorded in this manual. -
Page 56: Bios Features
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual BIOS Features • Supports Plug and Play V1.0A and DMI 2.3 • Supports Intel PCI (Peripheral Component Interconnect) (PME) local bus specification 2.2 • Supports Advanced Power Management (APM) specification v 1.1 • Supports ACPI •... - Page 57 Chapter 4: AMIBIOS The Main BIOS Setup Menu Press the <Delete> key during the POST (Power On Self Test) to enter the Main Menu of the BIOS Setup Utility. All Main Setup options are described in this section. The Main BIOS Setup screeen is displayed below. BIOS SETUP UTILITY Main Advanced Chipset PCIPnP...
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Page 58: Advanced Bios Setup
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Advanced BIOS Setup Choose Advanced BIOS Setup from the AMIBIOS Setup Utility main menu with the Left/Right arrow keys. You should see the following display. Select one of the items in the left frame of the screen, such as SuperIO Configuration, to go to the sub screen for that item. -
Page 59: Super Io Configuration
Chapter 4: AMIBIOS Super IO Configuration BIOS SETUP UTILITY Advanced Configure Winbond627F Serial Port(s) and Parallel P Serial Port1 Address [3F8] Serial Port1 IRQ Serial Port2 Address [2F8] Serial Port2 IRQ Serial Port2 Mode [Normal] Parallel Port Address [378] Parallel Port IRQ Parallel Port Mode [ECP] ECP Mode DMA Channel... -
Page 60: Ide Configuration
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Serial Port 2 Mode Use this option to choose the Serial Port 2 Mode. The settings are Normal, Sharp-IR, SIR and consumer. Parallel Port Address This option specifies the I/O address used by the parallel port. The settings for this item include Disabled, 378, 278 and 3BC. - Page 61 Chapter 4: AMIBIOS Primary IDE Master When entering "Setup", BIOS automatically detects the presence of IDE devices. This displays the auto detection status of the IDE de- vices. You can also manually configure the IDE drives by providing the following information: This option allows the user to configure the IDE devices.
- Page 62 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual PIO Mode IDE PIO (Programmable I/O) mode programs timing cycles between the IDE drive and the programmable IDE controller. As the PIO mode in- creases, the cycle time decreases. The settings are: Auto, 0, 1, 2, 3 and 4.
- Page 63 Chapter 4: AMIBIOS Primary IDE Slave When the system enters "Setup", BIOS automatically detects the presence of IDE devices. This option displays the auto detection status of IDE de- vices. The settings for "Primary IDE Slave" are the same as those for the "Primary IDE Master".
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Page 64: Floppy Configuration
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Floppy Configuration Floppy A Use this option to specify which of floppy drive you have installed in the A drive. The settings are Disabled, 360 KB 5 1/4", 1.2 MB 5 1/4", 720 KB 3 1/ 2", 1.44 MB 3 1/2"... - Page 65 Chapter 4: AMIBIOS allows the computer to force a third party BIOS to display during system boot. Keep Current has the system display AMIBIOS information on bootup. BootUp Num Lock This option is used to select the status of the Number Lock function on your keyboard on bootup.
- Page 66 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Wait for F1 if Error This settings for this option are Enabled and Disabled. Disabled: This prevents the AMIBIOS to wait on an error for user intervention. This setting should be used if there is a known reason for a BIOS error to appear. An example would be a system administrator must remote boot the system.
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Page 67: Event Log Configuration
Chapter 4: AMIBIOS Event Log Configuration Event Logging This option Enables or Disables the logging of events. You can use this screen to select options for the Event Log Configuration Settings. You can access sub screens to view the event log and mark all events as read. Use the up and down arrow keys to select an item, and the plus (+) and minus (-) keys to change the option setting. -
Page 68: Peripheral Device Configuration
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Peripheral Device Configuration Power Lost Control This option determines how the system will respond when power is reap- plied after a power loss condition. Choose Always On to automatically start up the system when power is reapplied. Always Off means you must push the main power button to restart the system after power is restored. -
Page 69: Chipset Setup
Chapter 4: AMIBIOS Chipset Setup Choose Chipset Setup from the AMIBIOS Setup Utility main menu. The screen is shown below. All Chipset Setup options are described following the screen. BIOS SETUP UTILITY Main Advanced Chipset PCIPnP Power Boot Security Exit Memory Timing Control [Auto] Options for MCH... -
Page 70: Pci Pnp Setup
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Hyper-threading Enables hyper-threading if supported by the operating system. Hyper- threading is a method of creating an additional "virtual" processor by using parallelism to process mulitple instructions simultaneously. The settings for this option are Enabled and Disabled. - Page 71 Chapter 4: AMIBIOS Plug & Play OS This option specifies how Plug and Play devices will be configured. settins are Yes and No. No lets BIOS configure all devices in the system. Yes lets the operating system (if supported) configure PnP devices not required for bootup.
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Page 72: Power Setup
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Power Setup Choose Power Setup from the AMIBIOS Setup main menu. All Power Setup options are described in this section. The Power Setup screen is shown below. BIOS SETUP UTILITY Main Advanced Chipset PCIPnP Power Boot Security Exit... - Page 73 Chapter 4: AMIBIOS ACPI Aware O/S This option allows the system to utilize Intel's ACPI (Advanced Configuration and Power Interface) specification. Settings are No and Yes. DOS®, Windows 3.x®, and Windows NT® are examples of non-ACPI aware oper- ating systems. Windows 95®, Windows 98®, Windows ME® and Windows 2000®...
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Page 74: Boot Setup
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Boot Setup Choose Boot Setup from the AMIBIOS Setup main menu. All Boot Setup options are described in this section. The Boot Setup screen is shown below. BIOS SETUP UTILITY Main Advanced Chipset PCIPnP Power Boot... - Page 75 Chapter 4: AMIBIOS 3rd Boot Device The settings for the 3rd Boot Device are Removable Device, ATAPI CDROM, Hard Drive, Onboard LAN2 Option-ROM and IBA 4.0.1.9 Slot 0102. 4th Boot Device The settings for the 4th Boot Device are Removable Device, ATAPI CDROM, Hard Drive, Onboard LAN2 Option-ROM and IBA 4.0.1.9 Slot 0102.
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Page 76: Security Setup
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Security Setup Choose Security Setup from the AMIBIOS Setup main menu. All Security Setup options are described in this section. The Security Setup screen is shown below. BIOS SETUP UTILITY Main Advanced Chipset PCIPnP Power Boot... - Page 77 Chapter 4: AMIBIOS Change Supervisor Password This option allows you to change a supervisor password that was entered previously. Change User Password This option allows you to change a user password that was entered previ- ously. Clear User Password Use this option to clear the user password so that it is not required to be entered when the system boots up.
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Page 78: 4-10 Exit Setup
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual 4-10 Exit Setup Choose Exit Setup from the AMIBIOS Setup main menu. All Exit Setup op- tions are described in this section. The Exit Setup screen is shown below. BIOS SETUP UTILITY Main Advanced Chipset PCIPnP... - Page 79 Chapter 4: AMIBIOS Load Optimal Defaults Highlighting this setting and then pressing <Enter> provides the optimum performance settings for all devices and system features. Load Failsafe Defaults Highlighting this setting and then pressing <Enter> provides the safest set of parameters for the system. Use them if the system is behaving errati- cally.
- Page 80 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Notes 4-26...
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Page 81: Appendix Abios Error Beep Codes
Appendix A: AMIBIOS Error Beep Codes Appendix A BIOS Error Beep Codes During the POST (Power-On Self-Test) routines, which are performed each time the system is powered on, errors may occur. Non-fatal errors are those which, in most cases, allow the system to continue the boot-up process. - Page 82 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Notes...
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Page 83: Appendix Bbios Post Checkpoint Codes
Appendix B: BIOS POST Checkpoint Codes Appendix B BIOS POST Checkpoint Codes When AMIBIOS performs the Power On Self Test, it writes checkpoint codes to I/O port 0080h. If the computer cannot complete the boot process, diagnostic equipment can be attached to the computer to read I/O port 0080h. Uncompressed Initialization Codes The uncompressed initialization checkpoint codes are listed in order of execution: Checkpoint... - Page 84 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Bootblock Recovery Codes The bootblock recovery checkpoint codes are listed in order of execution: Checkpoint Code Description The onboard floppy controller if available is initialized. Next, beginning the base 512 KB memory test. Initializing the interrupt vector table next.
- Page 85 Appendix B: BIOS POST Checkpoint Codes initialization before the keyboard BAT command is issued. The keyboard controller input buffer is free. Next, issuing the BAT command to the keyboard controller. The keyboard controller BAT command result has been verified. Next, performing any necessary initialization after the keyboard controller BAT command test.
- Page 86 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Checkpoint Code Description Interrupt vector initialization is done. Clearing the password if the POST DIAG switch is on. Any initialization before setting video mode will be done next. Initialization before setting the video mode is complete. Configuring the monochrome mode and color mode settings next.
- Page 87 Appendix B: BIOS POST Checkpoint Codes Checkpoint Code Description Patterns written in base memory. Determining the amount of memory below 1 MB next. The amount of memory below 1 MB has been found and verified. Determining the amount of memory above 1 MB memory next. The amount of memory above 1 MB has been found and verified.
- Page 88 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Checkpoint Code Description The DMA page register test passed. Performing the DMA Controller 1 base register test next. The DMA controller 1 base register test passed. Performing the DMA controller 2 base register test next. The DMA controller 2 base register test passed. Programming DMA controllers 1 and 2 next.
- Page 89 Appendix B: BIOS POST Checkpoint Codes Checkpoint Code Description Initializing the bus option ROMs from C800 next. See the last page of this chapter for additional information. Initializing before passing control to the adaptor ROM at C800. Initialization before the C800 adaptor ROM gains control has com- pleted.
- Page 90 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Notes...
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