Hitachi 15LD2200 Service Manual page 19

Signal Pin Type
FILT 23
HSYNC 65
VSYNC 64
DCLK 106 OSR
DCLKNEG 107 OSR
DVS 101
DHS 102
DEN 103
DER0 98 OSR
DER1 97 OSR
DER2 94 OSR
DER3 93 OSR
DER4 92 OSR
DER5 91 OSR
DER6 90 OSR
DER7 89 OSR
DEG0 88 OSR
15" TFT TV Service Manual
External PLL Loop Filter. When using the on-chip PLL, this pin must be connected to
AI
an external filter network.
Horizontal Synchronization Input. This digital input signal controls the horizontal scan
DIS frequency by synchronizing the start of the horizontal scan. The logic polarity of this
signal is controlled by the HSPOL bit.
Vertical Synchronization Input. This digital signal controls the vertical scan
DIS
frequency.
DPort Pixel Clock. Output clock for the display port pixel data. DCLK is enabled by
the DCLKEN bit and can be inverted by the DCPOL bit. DCLK can be set to run at ½
pixel rate, for dual pixel output mode, by setting the DCK2EN bit. The internal DCLK
clock domain can be disabled by the DCLKOFF bit to reduce power consumption.
DPort Pixel Clock.
DPort Vertical Sync. DVS can be either active-high or active-low depending on the
OS
VSPOL bit. Width and timing is controlled by the VPLSE and VDLY registers.
DPort Vertical Sync. DHS can be either active-high or active-low depending on the
OS
HSPOL bit. Sync width can be controlled by the HPLSE register.
DPort Pixel Enable. This signal is active whenever valid data is present. The polarity
OS
is specified by the DENPOL bit.
DEPort Red Pixel Data. In dual pixel output mode these pins are the EVEN red
outputs.
DEPort Green Pixel Data. In dual pixel output mode these pins are the EVEN green
outputs.
Function
17