Hitachi 15LD2200 Service Manual page 20

Signal Pin Type
DEG1 87 OSR
DEG2 86 OSR
DEG3 85 OSR
DEG4 82 OSR
DEG5 81 OSR
DEG6 80 OSR
DEG7 79 OSR
DEB0 78
DEB1 77
DEB2 74
DEB3 73
DEB4 71
DEB5 70
DEB6 67
DEB7 66
VCLK 72 I/O D5
VPEN 55 I/O D5
[56-
PORTD[0-7]
63]
15" TFT TV Service Manual
OSR
OSR
OSR
OSR
DEPort Blue Pixel Data. In dual pixel output mode these pins are the EVEN blue
outputs.
OSR
OSR
OSR
OSR
DVPort Pixel Clock. The VCLK pin is used for DV port image capture. The polarity
can be selected by the VCLKPOL bit.
DVPort Pixel Enable. Used when external flow control capture mode is enabled by
the EXTFCE bit. When VPEN is active, the input data is valid. The polarity can be
selected by the PENPOL bit. Use of this pin allows non-contiguous input data.
PORTD(7:0) can be used as GPO (Output Only).
I/O
Function
18