Block Diagram; Terminal Description - Integra RDC-7.1 Service Manual

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3 7 63 1515 0
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS
BU1924FS (RDS Decoder) <European model only>

BLOCK DIAGRAM

MUX
(4)
120k
(3)
Vref
V
DD1 (5)
Power supply
(6)
V
SS1
(12)
V
DD2
Power supply
(11)
V
SS2
TE
L 13942296513
XI
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100k
100k
anti-aliasing
filter
Analog
PLL
PLL
57kHz
1187.5Hz
RDS/ARI
Digital
Reference
clock
(13) (14)
XO

TERMINAL DESCRIPTION

Pin No. Pin name
1 QUAL
2 RDATA
3 Vref
4 MUX
5 V
DD1
6 V
SS1
7
V
SS3
8 CMP
9 T2
10 T1
11 V
SS2
12 V
DD2
13 XI
14 XO
15 (N.C.)
16 RCLK
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8
8th Switched
capacitor filter
Bi-phase
decoder
Measurement
circuit
(10)
Q Q
3 6 7 1 3
T1
Description
Output terminal of demodulator quality signal.
Output terminal of demodulator data.
Input terminal of reference voltage.
Input terminal of composite signal.
Analog power supply.
Analog power supply.
Ground.
Input terminal of comparator.
Input terminal for test mode.
Input terminal for test mode.
Digital power supply.
Digital power supply.
Connect to oscillator.
Connect to oscillator.
---
Output terminal of demodulator clock.
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.
2 9 9 4 2 8
V CMP
SS3
(7) (8)
comparator
RCLK
(16)
QUAL
(1)
RDATA
(2)
Differential
decoder
(9)
1 5 0 5 8 2 9 9 4
T2
m
co
TX-NR1000
9 9
2 8 9 9