Subsystem Configuration - Compaq EN Series Technical Reference Manual

3.2.3

SUBSYSTEM CONFIGURATION

The 443BX north bridge component provides the configuration function for the
processor/memory subsystem. Table 3-4 lists the configuration registers used for setting and
checking such parameters as memory control and PCI bus operation. These registers reside in the
PCI Configuration Space and accessed using the methods described in Chapter 4, section 4.2.
Table 3–4. Host/PCI Bridge Configuration Registers (443BX, Function 0)
Host/PCI Bridge Configuration Registers (82443BX, Function 0)
PCI Config.
Addr. Register
00, 01h Vender ID
02, 03h Device ID
04, 05h Command
06, 07h Status
08h Revision ID
09..0Bh Class Code
0Dh Latency Timer
0Eh Header Type
10..13h Aperture Base Config.
50, 51h PAC Config. Reg.
53h Data Buffer Control
55..56h DRAM Row Type
57h DRAM Control
58h DRAM Timing
59..5Fh PAM 0..6 Registers
60..67h DRAM Row Boundary
68h Fixed DRAM Hole
NOTES:
Refer to Intel Inc. documentation for detailed description of registers.
Assume unmarked locations/gaps as reserved.
Table 3-4.
Reset PCI Config.
Value Addr.
8086h 6A, 6Bh
7190h 6C..6Fh
0006h 70h
0210h 71h
-- 72h
-- 90h
00h 91h
00h 92h
8 93h
00h A0..A3h
83h A4..A7h
00h A8..ABh
01h B0..B3h
00h B4h
00h B8..BBh
01h BCh
00h BDh
Compaq Deskpro EN Series of Personal Computers
Net PC and Small Form Factor Models
First Edition - June 1998
Technical Reference Guide
Register
DRAM Control Reg.
Memory Buffer Strength
Multi-Transaction Timer
CPU Latency Timer
SMRAM Control
Error Command
Error Status Register 0
Error Status Register 1
Reset Control
AGP Capability Identifier
AGP Status
AGP Command
AGP Control
Aperture Size
Aperture Translation Table
Aperture I/F Timer
Low Priority Timer
Reset
Value
00h
55h
00h
1Fh
02h
00h
00h
00h
00h
N/A
N/A
00h
00h
0000h
0000h
00h
00h
3-9