Compaq EN Series Technical Reference Manual page 41

Processor Speed Selection
Changing the processor may require re-configuration of the bus/core frequency ratio. The system
board includes a six-position DIP switch (SW), of which four positions are used to select the bus-
to-core frequency ratio of the Pentium II. Table 3-2 shows the possible switch configurations for
this system and the resultant core (or processing) frequency, based on the Host bus frequency.
Table 3–2. Bus/Core Speed Switch Settings
Bus/Core Speed Switch Settings
DIP SW1 Settings Bus/Core
2 3 4 5 [1] Freq. Ratio
1 1 0 0
0 0 1 0
0 1 1 0
1 0 1 0
NOTES:
Not supported (possible thermal problems).
Celeron processor only
[1] 0 = Switch Closed (On), 1 = Switch Open (Off)
The processor reads the status of DIP SW1 positions 2-5 during the reset sequence to determine
the appropriate bus frequency. After the processor's RESET- signal becomes inactive, the DIP
SW1, 2-5 becomes inactive and the associated four signal lines are used by the processor for
IGNNE-, INTR-, A20M-, and NMI- respectively. Software can determine the operating speed
during run time by reading the bus speed from an MSR register in the processor.
NOTE: The DIP switch settings should be set to match the processor installed.
Configuring for a speed higher than that which the processor is designed could result in
unreliable operation and possible system damage.
Table 3-2.
Core Speed (MHz)
@66 MHz Bus
2/7 233
1/4 266
2/9 300
1/5 333
Compaq Deskpro EN Series of Personal Computers
Net PC and Small Form Factor Models
First Edition - June 1998
Technical Reference Guide
@100 MHz Bus
350
400
450
500
3-5