Intel Pentium Ii Processor; Figure 3-2. Pentium Ii Processor; Mmx Technology - Compaq EN Series Technical Reference Manual

3.2.1

INTEL PENTIUM II PROCESSOR

The Pentium II processor is packaged in a Single Edge Connector (SEC) cartridge that contains
the microprocessor and 512-KB ECC secondary (L2) cache (Figure 3-2). The cartridge installs
into a Slot 1-type connector on the system board, allowing easy replacing/upgrading of the
processor/cache memory complex.
Core processing speed
Figure 3–2. Pentium II Processor Internal Architecture
The Pentium II processor is software-compatible with earlier generation x86 microprocessors.
The microprocessor includes a dual-ALU MMX-supporting CPU, branch prediction logic, dual-
pipeline math coprocessor, and a 32-KB L1 cache that is split into two 16-KB 4-way, set-
associative caches for handling code and data separately.
The Pentium II processor includes 512 kilobytes of ECC SRAM for the write-through L2 cache.
Accesses with the L2 cache occur at half the processor core speed. The front side (Host) bus
interface of the 266-, 300-, and 333-MHz processors operates at 66-MHz. The Host bus interface
of the 350- and 400-MHz processors operates at 100 MHz.

3.2.1.1 MMX Technology

The CPU of the Pentium II supports 57 additional instructions for accelerating multimedia and
communications applications. Such applications often involve compute-intensive loops that can
take up as much as 90 percent of CPU execution time. The MMX logic, using a parallel
processing technique called Single Instruction-Multiple Data (SIMD), processes 64 bits of data at
a time. The MMX instructions are designed to take advantage of the dual-pipeline CPU as well
as help the programmer in avoiding branches in code. Specific applications that benefit from
MMX technology include 2D/3D graphics, audio, speech recognition, video codecs, and data
compression.
NOTE: MMX operations utilize a portion of the floating point registers of the
integrated math coprocessor. Programmers should avoid the mixing of MMX and
floating point code, which would reduce performance.
Pentium II Processor
CPU FPU 32-KB
L1
Cache
Branch FSB
Prediction I/F
½ Core processing speed
Compaq Deskpro EN Series of Personal Computers
Net PC and Small Form Factor Models
First Edition - June 1998
Technical Reference Guide
512-KB
L2
Cache
Host bus speed
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