Compaq EN Series Technical Reference Manual page 69

Table 4–12. Maskable Interrupt Priorities and Assignments
Maskable Interrupt Priorities and Assignments
Priority Signal Label
1 IRQ0
2 IRQ1
3 IRQ8-
4 IRQ9
5 IRQ10
6 IRQ11
7 IRQ12
8 IRQ13
9 IRQ14
10 IRQ15
11 IRQ3
12 IRQ4
13 IRQ5
14 IRQ6
15 IRQ7
-- IRQ2
Interrupts generated by PCI devices can be configured to share the standard AT (IRQn) interrupt
lines. Refer to section 4.2.5 "PCI Interrupt Mapping" for information on PCI interrupts.
Maskable Interrupt processing is controlled and monitored through standard AT-type I/O-
mapped registers. These registers are listed in Table 4-13.
Table 4–13. Maskable Interrupt Control Registers
Maskable Interrupt Control Registers
I/O Port Register
020h Base Address, Int. Cntlr. 1
021h Initialization Command Word 2-4, Int. Cntlr. 1
0A0h Base Address, Int. Cntlr. 2
0A1h Initialization Command Word 2-4, Int. Cntlr. 2
The initialization and operation of the interrupt control registers follows standard AT-type
protocol.
Table 4-12.
Source (Typical)
Interval timer 1, counter 0
Keyboard
Real-time clock
Spare and ISA connector pin B04
Spare and ISA connector pin D03
Spare and ISA connector pin D04
Mouse and ISA connector pin D05
Coprocessor (math)
IDE primary I/F and ISA connector pin D07
IDE secondary I/F and ISA connector pin D06
Serial port (COM2) and ISA connector pin B25
Serial port (COM1) and ISA connector pin B24
ISA connector pin B23
Diskette drive controller and ISA connector pin B22
Parallel port (LPT1)
NOT AVAILABLE (Cascade from interrupt controller 2)
Table 4-13.
Compaq Deskpro EN Series o Personal Computers
Net PC and Small Form Factor Models
First Edition - June 1998
Technical Reference Guide
4-23