Panel Interface - NEC LCD1550X Service Manual

1.7

Panel interface

• Timing for panel power and interface signal
PANEL5V
Interface signal
(3.3V system)
The following is set to satisfy the following panel AC timing with the microcomputer timing
control.
<
t1 40ms
=
<
0ms < t2 50ms
=
< =
0ms < t3 3ms
< =
0ms < t4 3ms
< =
0ms < t5 50ms
< =
0ms < t6 1s
t7 0.2s
• DC characteristics of interface signal.
The ASIC (Maurice2) clock delay time is set so that the panel clock's falling edge hits at the
center of the data.
QCLK
QDE, QHD,
QVD, DATA
The timing reference is 1.5V.
Note that the panel input Hi level voltage (VIH) and panel input Lo level voltage (VIL) are as
follows.
< =
VIH 2.0V, VIL 0.8V (TTL level)
Maurice2's panel output level is VOH
connection is possible.
* D3_3V is Maurice2's I/O power 3.3V.
t t t
1 2 3
TSTC
1.5V
t t t
4 5 6
1.5V
THTC
1.5V
D3_3V-0.05V and VOL
1 - 40
t
7
<
0.05V, and thus direct
=