Processor Cards - IBM OpenPower 720 Technical Overview And Introduction

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consumption, and decreased IT footprint size through logical partitioning. The POWER5

processor chip takes advantage of IBM leadership technology. It is made using IBM

0.13-

m-lithography CMOS technology. The POWER5 processor also uses copper and

silicon-on-insulator (SOI) technology to allow a higher operating frequency for improved

performance yet with reduced power consumption and improved reliability compared to

processors not using this technology.

2.2 Processor cards

In the OpenPower system, the POWER5 chip has been packaged with the L3 cache chip (on

2-way cards) into a cost-effective Dual Chip Module (DCM) package. The storage structure

for the POWER5 chip is a distributed memory architecture, which provides high memory

bandwidth. Each processor can address all memory and sees a single shared memory

resource. As such, a single DCM and its associated L3 cache and memory are packaged on

a single processor card. Access to memory behind another processor is accomplished

through the fabric buses. The OpenPower 720 supports up to two processor cards (each card

is a 2-way) or a single 1-way card. Each 2-way processor card has a single DCM containing a

POWER5 processor chip and a 36 MB L3 module. On all cards I/O connects to the Central

Electronic Complex (CEC) subsystem through the GX+ bus. Each DCM provides a single

GX+ bus for a total system capability of two GX+ buses. The GX+ bus provides an interface to

a single device such as the RIO-2 buses, as shown in Figure 2-4.

GX+ Controller

Figure 2-4 OpenPower 720 DCM diagram

Each processor card contains a single DCM and the local memory storage subsystem for that

DCM. The processor card also contains LEDs for each FRU

CPU card itself. See Figure 2-5 on page 24 for a processor card layout view.

Field Replacement Unit

core

1.9 MB L2

L3 Cache

Data Unit

36 MB

SMI II

on the CPU card including the

Chapter 2. Architecture and technical overview

DIMM

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