Pioneer PDP-501MX Service Manual page 71

¶ Pin Function
PIN NO. PIN NAME
1 REFL Y
2 CY
3 SUB
4 UV0
5 UV1
6 UV2
7 UV3
8 UV4
9 UV5
10 UV6
11 UV7
12 VDD D1
13 VSS D1
14 Y0
15 Y1
16 Y2
17 Y3
18 Y4
19 Y5
20 Y6
21 Y7
22 AP
23 SP
24 MC
25 LLC
26 HREF
27 RESET
28 SCL
29 SDA
30 VSS D2
31 VDD D2
32 VDD A1
33 (R-Y)
34 VSS A1
35 VSS A2
36 (B-Y)
37 VDD A2
38 VSS A2
39 Y
40 VDD A3
41 CUR
42 VDD A4
43 C UV
44 REF L UV
Low reference of luminance DAC (connected to VSS A1)
Capacitor for luminance DAC (high reference)
Substrate (connected to VSS A1)
UV signal input bit UV7 (digital colour-difference signal)
UV signal input bit UV6 (digital colour-difference signal)
UV signal input bit UV5 (digital colour-difference signal)
UV signal input bit UV4 (digital colour-difference signal)
UV signal input bit UV3 (digital colour-difference signal)
UV signal input bit UV2 (digital colour-difference signal)
UV signal input bit UV1 (digital colour-difference signal)
UV signal input bit UV0 (digital colour-difference signal)
+5V digital supply voltage 1
Digital ground 1(0 V)
Y signal input bit Y7 (digital luminance signal)
Y signal input bit Y6 (digital luminance signal)
Y signal input bit Y5 (digital luminance signal)
Y signal input bit Y4 (digital luminance signal)
Y signal input bit Y3 (digital luminance signal)
Y signal input bit Y2 (digital luminance signal)
Y signal input bit Y1 (digital luminance signal)
Y signal input bit Y0 (digital luminance signal)
Connected to ground (action pin for testing)
Connected to ground (shift pin for testing)
Data cloack CREF(e.g.13.5MHz);at MC=HIGH,the LLC driver-by-two is inactive
Line-locked clock signal(LL27=27MHz)
Data clock for YUV data inputs (for active line 768Y or 640Y long)
Reset input (active LOW)
2
I C-bus clock line
I 2 c-bus data line
Digital ground 2(0V)
+5V digital supply voltage 2
+5V analog supply voltage for buffer of DAC 1
±(R-Y)output signal (analog signal)
Analog ground 1(0V)
Analog ground 2(0V)
±(B-Y)output signal (analog colour-difference signal)
+5V analog supply voltage for buffer of DAC 2
Analog ground 3 (0V)
Y output signal(analog luminance signal)
+5V analog supply voltage for buffer of DAC 3
Current input for analog output buffers
Supply and reference voltage for the three DAC S
Capacitor for chrominance DAC S(high reference)
Low reference of chrominance DAC S(connected to VSS A1 )
PDP-501MX, PDP-V501X
PIN FUNCTION
71