Pioneer PDP-501MX Service Manual page 70

PDP-501MX, PDP-V501X
Pin No. Pin Name
51 VDD 6
52 VSS 6
53 YUV D3
54 YUV D4
55 YUV D5
56 YUV D6
57 YUV D7
58 VDD 7
59 VSS 7
60 SNRST
61 SNDA
62 SNCL
63 AUX
64 Ho
65 NC
66 NC
67 YUV A7
68 YUV A6
69 YUV A5
70 YUV A4
71 YUV A3
72 YUV A2
73 VSS 8
74 VDD 8
75 YUV A1
76 YUV A0
77 YUV A11
78 YUV A10
79 YUV A9
80 YUV A8
7
ASAA7165WP
(PROGRESSIVE BLOCK : IC4702)
VIDEO ENHANCEMENT D/A
¶ Pin Assignment
6 5 4 3 2 1
7
UV3
8
UV4
9
UV5
10
UV6
UV7 11
SAA7165
V
DDD1 12
V
SSD1 13
14
Y0
15
Y1
16
Y2
17
Y3
20 21 22 23
18 19
70
TYPE
Supply voltage 6
S
Ground 6
G
Y bit 3
O
Y bit 4
O
O Y bit 5
Y bit 6
O
Y bit 7
O
Supply voltage 7
S
Ground 7
G
I Field frequent reset from microcontroller;reset for SNERT interface
Data for SNERT interface
I/O
Clock for SNERT interface
I
Spre output form line-sequencer
O
Output hold to e.g.LC.display
O
- Not connected
Not connected
-
Y bit 7 from FM1
I
Y bit 6 from FM1
I
Y bit 5 from FM1
I
I Y bit 4 from FM1
Y bit 3 from FM1
I
I Y bit 2 from FM1
Ground 8
G
Supply voltage 8
S
Y bit 1 from FM1
I
Y bit 0 from FM1
I
I UV bit 3 from FM1
UV bit 2 from FM1
I
UV bit 1 from FM1
I
UV bit 0 from FM1
I
¶ Block Diagram
44 43 42 41 40
YUV-bus
39
Y
38 V
SSA3
37
V
DDA2
36 (B - Y)
35 V
SSA2
34 V
SSA1
2
I C-bus
33 (R - Y)
32 V
DDA1
V
31 DDD2
30
V SSD2
29 SDA
24 25 26
27 28
Pin Function
V DDD1 V DDD2
12 31
Y7 to Y0
21 to 14
PEAKING
Y
8
AND
FORMATTER
CORING
data clock
UV7 to
UN0 11 to 4
UV
INTERPOLATION
8
FORMATTER FILTER
MC 24
TIMING
LLC
25
CONTROL
HREF 26
RESET
27
SCL
28
2
TEST
I C-BUS
CONTROL
SDA CONTROL
29
13 30 22
V V AP
SSD1 SSD2
V DDA1 V DDA2 V DDA3 CUR V
DDA4
32 37 40 41 42
25
Y
DAC 3
DATA
25
SWITCH
U
DAC 2
DCTI
V
DAC 1
25
SAA7165
23 3 34 35 38
SP SUB V V V
SSA1 SSA2 SSA3
2
C
Y
39 Y
1 REFL
Y
36 (B - Y)
44 REFL
UV
43
C UV
33 (R - Y)