Pioneer PDP-501MX Service Manual page 48

PDP-501MX, PDP-V501X
7
CXA3106Q
(DIGITAL VIDEO ASSY: IC1242)
PLL IC
¶ Pin Assignment
36 35 34 33
37
IOGND
38
IOVcc
PLLVcc 39
PLLGND 40
VCOVcc 41
VCOGND 42
VCOHGND 43
IREF 44
RC2 45
RC1 46
IRGND 47
48
IRVcc
1 2 3 4
¶ Block Diagram
VCO
TTL IN
(TTL)
VCO
PECL IN
(PECL)
SYNC
TTL IN
(TTL)
Polarity
SYNC
PECL IN
(PECL)
1bit
HOLD
TTL IN
(TTL)
DAC
CONTROL REGISTER
IRFF
SENABLE
48
32 31 30 29 28 27 26 25
CXA3106Q
5 6 7 8 9 10 11 12
RC1 RC2
1/16~20/16 CLK
Charge
Phase Fine
Pump
Detector Delay
2bit
1bit
on/off 1bit on/off 1bit
read out
TTL OUT
SCLK SDATA
SER OUT
24
DSYNC
23
CLK
22
CLKN
21 CLK/2
CLK/2N
20
19 DGND
18 DVcc
17 UNLOCK
16 DIVOUT
15
SEROUT
14 CS
13 TLOAD
Latch
Logic
MUX
VCO DIV
5bit
1bit 2bit
1/256~1/4096 CLK
Programmable
Counter
12bit
synthesizer
power save
TTL OUT TTL IN
DIV OUT TLOAD
on/off 1bit
1~4 CLK
TTL OUT
Coarse
Polarity
Delay
PECL OUT
2bit 1bit
on/off 1bit
TTL OUT
on/off 1bit
TTL OUT
PECL OUT
on/off 1bit
TTL OUT
on/off 1bit
RSET TTL OUT
1/2
PECL OUT
on/off 1bit
unlock
detect
PECL
whole chlp
power save
1bit
CS
DSYNC
(TTL)
DSYNC
(PECL)
CLK
(TTL)
NCLK
(TTL)
CLK
(PECL)
CLK/2
(TTL)
NCLK/2
(TTL)
CLK/2
(PECL)
UNLOCK
VBB