Sony STR-DA5300ES Service Manual page 146

STR-DA5300ES
DSP BOARD IC5208 MB91F353APMT-07A53DSP-X103 (DSP CONTROLLER)
Pin No. Pin Name
1
RDATA0
2 to 8 -
9
DSP2_SIB_SEL
10
P_ERROR
11
DSP1_SPIDS
12
DSP1_RESET
DSP1_
BOOTCFG0,
13, 14
DSP1_
BOOTCFG1
15, 16 -
17 SF2_DSP2_MAS
18, 19 -
20
SF2_CPU_CE
21
DSP2_SPIDS
22
DSP2_RESET
23, 24 -
DSP2_
BOOTCFG0,
25, 26
DSP2_
BOOTCFG1
27 to 35 -
36
DRST_TRG
37 to 39 -
40 VSS
41, 42 -
43
VSS
44
VCC
45 to 47 -
48
RD
49 WR0
50, 51 -
52 MD2
53, 54
MD1, MD0
55
XRESET
56
VCC
57 XOUT
58
XIN
59
VSS
60 to 62 -
63 MD_BUSY
64
DM_BUSY
65 DM_INT
66 to 69 -
70, 71 PN0, PN2
72 to 75 -
76
VSS
146
I/O
I Audio serial data input from the digital audio interface receiver
-
Not used
O Data selection signal output to the data selector
I PLL lock error signal and data error flag input from the DSP1
O Serial data latch pulse signal output to the DSP1
O Reset signal output to the DSP1 and flash memory "L": reset
O Boot mode setting signal output to the DSP1
-
Not used
I
Master/slave selection signal input from the DSP2
-
Not used
O Chip enable signal output to the serial flash
O Serial data latch pulse signal output to the DSP2
O Reset signal output to the DSP2 "L": reset
- Not used
O Boot mode setting signal output to the DSP2
-
Not used
I Programming end flag input from the system controller
-
Not used
- Ground terminal
-
Not used
- Ground terminal
- Power supply terminal (+3.3V)
- Not used
-
Not used
-
Not used
-
Not used
I Programming mode signal input from the system controller
I Programming mode signal input terminal Not used
I Reset signal input from the system controller "L": reset
- Power supply terminal (+3.3V)
O System clock output terminal (12.5 MHz)
I System clock input terminal (12.5 MHz)
- Ground terminal
-
Not used
I Busy signal input from the system controller
O Busy signal output to the system controller
O Interrupt request signal output terminal Not used
-
Not used
- Not used
-
Not used
- Ground terminal
Description