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Table 2-1 summarizes the technology characteristics of the POWER7 processor.
Table 2-1 Summary of POWER7 processor technology
Technology
Die size
Fabrication technology
Components
Processor cores
Max execution threads core/chip
L2 cache per core/per chip
On-chip L3 cache per core/per chip
DDR3 memory controllers
SMP design-point
Compatibility
2.2.2 POWER7 processor core
Each POWER7 processor core implements aggressive out-of-order (OoO) instruction
execution to drive high efficiency in the use of available execution paths. The POWER7
processor has an instruction sequence unit that is capable of dispatching up to six
instructions per cycle to a set of queues. Up to eight instructions per cycle can be issued to
the instruction execution units. The POWER7 processor has a set of twelve execution units
as follows:
2 fixed point units
2 load store units
4 double precision floating point units
1 vector unit
1 branch unit
1 condition register unit
1 decimal floating point unit
The caches that are tightly coupled to each POWER7 processor core are as follows:
Instruction cache: 32 KB
Data cache: 32 KB
L2 cache: 256 KB, implemented in fast SRAM
L3 cache: 4MB eDRAM
POWER7 processor
2
567 mm
45 nm lithography
Copper interconnect
Silicon-on-Insulator
eDRAM
1.2 billion components (transistors) offering the equivalent
function of 2.7 billion (For further details, see 2.2.6, "On-chip
L3 intelligent cache" on page 44)
8
4/32
256 KB / 2 MB
4 MB / 32 MB
2
Up to 32 sockets with IBM POWER7 processors
With prior generation of POWER processor
Chapter 2. Architecture and technical overview
41
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