General-Purpose In/Outputs - Marantz SA12 Service Manual

RESETn is an asynchronous reset and should be low for at
least 1 period of DSD_CLK.

General-purpose in/outputs.

Four general purpose input and output signals are available.
IC-Pin_no Name
1 H_DQ[13]
2 H_DQ[12]
3 VCC_IO
4 GND_IO
5 H_DQ[11]
6 H_DQ[10]
7 H_DQ[9]
8 H_DQ[8]
9 H_DQ[7]
10 H_DQ[6]
11 H_DQ[5]
12 H_DQ[4]
13 VCC_CORE
14 GND_CORE
15 H_DQ[3]
16 H_DQ[2]
17 H_DQ[1]
18 H_DQ[0]
19 VCC_IO
20 H_procclock
21 GND_IO
22 H_WAIT
23 H_RWn
24 H_CSLn
25 H_CSHn
26 H_ben(1)
27 H_ben(0)
28 B_V4
29 B_SYNC
30 B_FLAG
31 B_BCLK
32 B_WCLK
33 B_DATA
34 GP_in_pin(0)
35 GP_in_pin(1)
36 AD[6]
37 AD[5]
38 AD[4]
39 VCC_CORE
40 GND_CORE
41 AD[3]
42 AD[2]
43 AD[1]
44 AD[0]
45 GP_in_pin (2)
46 biasin
47 vddaagc
48 Agcadctstp
49 vssaagc
50 agcinp
51 VCC_IO
52 GND_IO
53 agcadctstn
54 vssaadc
55 vddaadc
56 adcrefh
57 Adcrefm
Type Function
I/O5 Data bus
I/O5 Data bus
IN 3.3V power supply IO
IN Ground
I/O5 Data bus
I/O5 Data bus
I/O5 Data bus
I/O5 Data bus
I/O5 Data bus
I/O5 Data bus
I/O5 Data bus
I/O5 Data bus
IN 3.3V power supply Core
IN Ground(core)
I/O5 Data bus
I/O5 Data bus
I/O5 Data bus
I/O5 Data bus
IN 3.3V power supply IO
IN Host processor EMI interface clock
IN Ground
O5 Wait signal
IN READ=1,Write=0
IN Chip Select, active low
IN Chip select
IN Byte Enable 1
IN Byte Enable 0
IN Versatile Input Pin (contains Subcode), not used
IN Sector sync / Absolute time sync
IN I2S flag (EDC flag)
IN I2S Bit ClocK
IN I2S Word CLock
IN I2S Data
IN General purpose in
IN General purpose in
I/O5
I/O5
I/O5
IN 3.3V power supply Core
IN Ground(core)
I/O5
I/O5
I/O5
I/O5 Digital out of AD OR digital in for PLL
IN General purpose in
APIO Current input. connect via 15K to VSS
VDDCO VDD of AGC ( + 3.3V)
APIO AGC Positive channel test pin
VSSCO Analog ground for AGC.
APIO AGC positive input signal, HF in.
IN 3.3V power supply IO
In Ground
APIO AGC Negative channel test pin
VSSCO VSS of AGC & ADC connected to substrate
VDDCO VDD of ADC ( +3.3V)
APIO ADC decoupling high . (via 100nF to VSS)
APIO ADC decoupling middle . (via 100nF to VSS)
9.24.6 Pin description
177