Appendix B - Post Codes - Diamond Multimedia Micronics C400 Manual

C400 pentium ii system board
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Appendix
POST Codes
B
The following tables list the Power On Self Test (POST)
codes, names and solutions. EISA POST codes are typically
output to port address 300h. ISA POST codes are output
to port address 80h.
Code
Name
(hex)
C0
Turn Off Chipset Cache
1
Processor Test 1 Verification
2
Processor Test 2
3
Initialize Chips
4
Test Memory Refresh Toggle
5
Blank video, Initialize keyboard
6
Reserved
7
Test CMOS Interface and Battery
Status
BE
Chipset Default Initialization
C1
Memory presence Test
C5
Early Shadow
C6
Cache presence test
8
Setup low memory
9
Early Cache Initialization
A
Setup Interrupt Vector Table
B
Test CMOS RAM Checksum
C
Initialize Keyboard
D
Initialize Video Interface
E
Test Video Memory
F
Test DMA
Micronics C400 System Board Manual
Appendix B: POST Codes
Description
OEM Specific-Cache control
Processor Status (1FLAGS) Tests the following
processor status flags: carry, zero, sign, overflow, The
BIOS sets each flag, verifies they are set, then turns
each flag off and verifies it is off.
Read/Write/Verify all CPU registers except SS, SP, and
BP with data pattern FF and 00.
Disable NMI, PIE, AIE, UEI, SQWV Disable video,
parity checking, DMA. Reset math coprocessor. Clear
all page registers, CMOS shutdown byte. Initialize timer
0, 1, and 2, including set EISA timer to a known state.
Initialize DMA controllers 0 and 1 Initialize interrupt
controllers 0 and 1 Initialize EISA extended registers.
RAM must be periodically refreshed to keep the
memory from decaying. This function ensures that the
memory refresh function is working properly.
Keyboard controller initialization.
Verifies CMOS is working correctly,
Program chipset registers with power on BIOS defaults.
OEM Specific-Test to size on-board memory
OEM Specific-Early Shadow enable for fast boot.
External cache size detection
Early chip set initialization. Memory presence test.
OEM chip set routines. Clear low 64K of memory. Test
first 64K memory.
Cyrix CPU initialization Cache initialization
Initialize first 120 interrupt vectors with
SPURIOUS_INT_HDLR and initialize INT 00h-1Fh
according to INT_TBL
Test CMOS RAM Checksum, if bad, or insert key
pressed, load defaults.
Detect type of keyboard controller (optional)x Set
NUM_LOCK status.
Detect CPU clock. Read CMOS location 14h to find out
type of video in use. Detect and Initialize Video
Adapter.
Test video memory, write sign-on message to screen.
Setup shadow RAM - Enable shadow according to
Setup.
BIOS checksum test. Controller 0 Keyboard detect and
67

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