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However, if any program writes to this memory area, a
system error may result.
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM
at C0000h to C7FFFh, resulting in better video perfor-
mance. However, if any program writes to this memory
area, a system error may result.
8-Bit/16-Bit I/O Recovery Time
The I/O recovery mechanism adds bus clock cycles be-
tween PCI-originated I/O cycles to the ISA bus. This delay
takes place because the PCI bus is so much faster than the
ISA bus. These two fields let you add recovery time (in bus
clock cycles) for 16-bit and 8-bit I/O.
Video RAM Cacheable
Enable or disable the caching of the video RAM. The
default settings is Disabled.
Memory Hole at 15M-16M
You can reserve this area of system memory for the ISA
adapter ROM. When this area is reserved, it cannot be
cached.
Passive Release
When enabled, CPU to PCI bus accesses are allowed
during passive release. Otherwise, the arbiter only accepts
another PCI master access to local DRAM.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to
support delay transaction cycles. Select Enabled to sup-
port compliance with PCI specification version 2.1.
Micronics C400 System Board Manual
Chapter 4: The BIOS Setup Utility
41
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