Absolute Maximum Ratings; Thermal Resistance; Explanation Of Test Levels; Esd Caution - Analog Devices AD9854 User Manual

AD9854

ABSOLUTE MAXIMUM RATINGS

Table 2.
Parameter
Maximum Junction Temperature
V
S
Digital Inputs
Digital Output Current
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Maximum Clock Frequency (ASVZ)
Maximum Clock Frequency (ASTZ)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

The heat sink of the AD9854ASVZ 80-lead TQFP package must
be soldered to the PCB.
Table 3.
Thermal Characteristic
1, 2, 3
θ (0 m/sec airflow)
JA
2, 3, 4, 5
θ (1.0 m/sec airflow)
JMA
2, 3, 4, 5
θ (2.5 m/sec airflow)
JMA
Ψ
1, 2
JT
6, 7
θ
JC
1
Per JEDEC JESD51-2 (heat sink soldered to PCB).
2
2S2P JEDEC test board.
Values of θ
3
are provided for package comparison and PCB design
JA
considerations.
4
Per JEDEC JESD51-6 (heat sink soldered to PCB).
5
Airflow increases heat dissipation, effectively reducing θ
more metal that is directly in contact with the package leads from metal
traces through holes, ground, and power planes, the more θ
6
Per MIL-Std 883, Method 1012.1.
Values of θ
7
are provided for package comparison and PCB design
JC
considerations when an external heat sink is required.
Rating
150°C
4 V
−0.7 V to +V
S
5 mA
−65°C to +150°C
−40°C to +85°C
300°C
300 MHz
200 MHz
TQFP LQFP
16.2°C/W 38°C/W
13.7°C/W
12.8°C/W
0.3°C/W
2.0°C/W
. Furthermore, the
JA
is reduced.
JA
Rev. E | Page 8 of 52
To determine the junction temperature on the application PCB
use the following equation:
Ψ
T = T + ( × PD)
J case JT
where:
T is the junction temperature expressed in degrees Celsius.
J
T is the case temperature expressed in degrees Celsius, as
case
measured by the user at the top center of the package.
Ψ
= 0.3°C/W.
JT
PD is the power dissipation (PD); see the Power Dissipation and
Thermal Considerations section for the method to calculate PD.

EXPLANATION OF TEST LEVELS

Table 3.
Test Level Description
I 100% production tested.
III Sample tested only.
IV
Parameter is guaranteed by design and
characterization testing.
V Parameter is a typical value only.
VI Devices are 100% production tested at 25°C and
guaranteed by design and characterization testing
for industrial operating temperature range.

ESD CAUTION