Analog Devices AD9854 User Manual page 28

AD9854
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Continue chirp by immediately returning to the beginning
frequency (F1) in a sawtooth fashion, and then repeating the
previous chirp process using the CLR ACC1 control bit.
An automatic, repeating chirp can be set up by using the
32-bit update clock to issue the CLR ACC1 command at
precise time intervals. Adjusting the timing intervals or
changing the delta frequency word changes the chirp
range. It is incumbent upon the user to balance the chirp
duration and frequency resolution to achieve the proper
frequency range.
BPSK (Mode 100)
Binary, biphase, or bipolar phase shift keying is a means to
rapidly select between two preprogrammed 14-bit output phase
offsets that equally affect both the I and Q outputs of the
AD9854. The logic state of Pin 29, the BPSK pin, controls the
selection of Phase Adjust Register 1 or Phase Adjust Register 2.
When low, Pin 29 selects Phase Adjust Register 1; when hig
selects Phase Adjust Register 2. Figure 48 illustrate
changes made to four cycles of an out
Basic BPSK Programming Steps
1. Program a carrier frequency into Frequency Tuning Word 1.
2. Program the appropriate 14-bit phase words int
Adjust Register 1 and Phase Adjust Regi
3. Attach the BPSK data source to Pin 29.
4. Activate the I/O update clock when ready.
Note that for higher-order PSK modulation, the user can sele
the single-tone mode and program Phase Adjust Register
using the serial or high speed parallel programming bus.
Rev. E | Page 28 of 52
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