Analog Devices AD9854 User Manual page 33

1
Table 8. Register Layout
Parallel Serial
Address Address
(Hex) (Hex) Bit 7
00 0 Phase Adjust Register 1 <13:8> (Bits 15, 14, don't care)
01 Phase Adjust Register 1 <7:0>
02 1 Phase Adjust Register 2 <13:8> (Bits 15, 14, don't care)
03 Phase Adjust Register 2 <7:0>
04 2 Frequency Tuning Word 1 <47:40>
05 Frequency Tuning Word 1 <39:32>
06 Frequency Tuning Word 1 <31:24>
07 Frequency Tuning Word 1 <23:16>
08 Frequency Tuning Word 1 <15:8>
09 Frequency Tuning Word 1 <7:0>
0A 3 Frequency Tuning Word 2 <47:40>
0B Frequency Tuning Word 2 <39:32>
0C Frequency Tuning Word 2 <31:24>
0D Frequency Tuning Word 2 <23:16>
0E Frequency Tuning Word 2 <15:8>
0F Frequency Tuning Word 2 <7:0>
10 4 Delta frequency word <47:40>
11 Delta frequency word <39:32>
12 Delta frequency word <31:24>
13 Delta frequency word <23:16>
14 Delta frequency word <15:8>
15 Delta frequency word <7:0>
16 5 Update clock <31:24>
17 Update clock <23:16>
18 Update clock <15:8>
19 Update clock <7:0>
1A 6 Ramp rate clock <19:16> (Bits 23, 22, 21, 20, don't care)
1B Ramp rate clock <15:8>
1C Ramp rate clock <7:0>
1D 7 Don't
care
CR [31]
1E Don't
care
1F CLR
ACC 1
20 Don't
care
21 8 Output shaped keying I multiplier <11:8> (Bits 15, 14, 13, 12 don't care)
22 Output shaped keying I multiplier <7:0>
23 9 Output shaped keying Q multiplier <11:8> (Bits 15, 14, 13, 12 don't care)
24 Output shaped keying Q multiplier <7:0>
25 A Output shaped keying ramp rate <7:0>
26 B QDAC <11:8> (Bits 15, 14, 13, 12 don't care)
27 QDAC <7:0> (data is required to be in twos complement format)
1
The shaded sections comprise the control register.
AD9854 Register Layout
Bit 6 Bit 5 Bit 4
Don't Don't Comp
care care PD
PLL Bypass Ref
range PLL Mult 4
CLR Triangle SRC
ACC 2 QDAC
Bypass OSK EN OSK
inv sinc INT
Rev. E | Page 33 of 52
Bit 3 Bit 2
Phase 1
Phase 2
Freq 1
Reserved, QDAC PD
always low
Ref Mult 3 Ref Mult 2
Mode 2 Mode 1
Don't care Don't care
Bit 1 Bit 0
DAC PD DIG PD
Ref Ref Mult 0
Mult 1
Mode 0 Internal/external
update clock
LSB first SDO active CR [0]
AD9854
Default
Value
(Hex)
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
40
00
00
00
10
64
01
20
00
00
00
00
80
00