Analog Devices AD9854 User Manual page 14

AD9854
Figure 16 and Figure 17 show the narrow-band performance of the AD9854 when operating with a 200 MHz reference clock with the
REFCLK multiplier bypassed vs. a 20 MHz reference clock and the REFCLK multiplier enabled at 10×.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
CENTER 39.1MHz
Figure 16. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
200 MHz REFCLK with REFCLK Multiplier Bypassed
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
CENTER 39.1MHz
Figure 17. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
20 MHz REFCLK with REFCLK Multiplier = 10×
–100
–110
–120
–130
–140
–150
A = 5MHz
–160 OUT
–170
10 100 1k
FREQUENCY (Hz)
Figure 18. Residual Phase Noise,
300 MHz REFCLK with REFCLK Multiplier Bypassed
5kHz/ SPAN 50kHz
5kHz/ SPAN 50kHz
A = 80MHz
OUT
10k 100k 1M
–90
–100
–110
–120
–130
–140
–150
A
OUT
–160
10
30 MHz REFCLK with REFCLK Multiplier = 10×
55
54
53
52
51
50
49
48
0
Figure 20. SFDR vs. DAC Current, 59.1 A
300 MHz REFCLK with REFCLK Multiplier Bypassed
620
615
610
605
600
595
590
0
Figure 21. Supply Current vs. Output Frequency (Variation Is Minimal,
Expressed as a Percentage, and Heavily Dependent on Tuning Word)
Rev. E | Page 14 of 52
A = 80MHz
OUT
= 5MHz
100 1k 10k
FREQUENCY (Hz)
Figure 19. Residual Phase Noise,
5 10 15
DAC CURRENT (mA)
20 40 60 80 100
FREQUENCY (MHz)
100k 1M
20 25
,
OUT
120 140