Epson PC AX Technical Manual page 190

DIAGRAMS AN» REFERENCE MATERIALS
REV.A
7.2.6 GAATIO
GAATIO includes following functional blocks.
(1) Address decoder of 1/0 space.
(2) D~~ page register (741S612 compatible)
(3)
Port B.
(4) ~~I enable register.
(5) Address latch for D~.
(6) Interface circuit between NP (80287) and CPU (80286).
(7) General purpose gates.
--- 1 inverter, 1 NANO gate, two 3-state buffers.
TABU 7-2-10. GAATIO PIN DESCRIPTION
SYMBOL 1/0* PIB NO. NAME AND FUNCTION
STB2 I
STB1 I
AE01 0
MSTN I
Internal data bus.
CPU address bus.
>
>
>
Internal address bus.
>
>
(-) Internal 1/0 write signal.
(=
-XIOW)
(-) Internal 1/0 read signal.
(=
-XIOR)
(-) Reset.
-DACK7.
D~~
acknowledge 7.
-DACK6.
D~~
acknowledge 6.
-DACK4.
D~~
acknowledge 4.
-DACK3,
D~
acknowledge 3.
-DACK2.
D~
acknowledge 2.
-DACKO.
D~
acknowledge O.
+DACK4. This signal is output.
(-) Refresh signal.
(-)
D~
acknowledge. ACKN is active when DMA or
refresh cycle is being performed.
(+) DHAC-N02 (16-bit
D~
controller) address
strobe signal.
(+) DMAC-N01 (8-bit DMA controller) address
strobe signal.
(+) Address enable signal of D~C-N02.
(+) Address enable signal of DMAC-N01.
(-) AE02 is active when
D~~C-N02
has control of
the system.
(-) AE01 is active when
D~C-N01
has control of
the system.
-t~STER.
When low, it indicates that the master
on the option slot (DMAC or CPU on the slot) has
the control of the system.
27
26
38-31
66,68,70,72,
74,76,80
77,75,73,71,
69,67 ,64
62,63
61-55
52
12
11
30
21
20
19
18
17
16
14
85
86
22
23
96
87
97
Tri
O&H-Z
XD7-0
A23-17
AEN2 I
AEN1 I
AE02 0
XA16-10 O&H-Z
XA9-8 Tri
XA7-1 I
XAO
I
XIWN I
XIRN I
RSTN I
DK7N I
DK6N I
DK4N I
DK3N I
DK2N
I
DKON
I
DAK4
I
RFHN I
ACKN I
7-16