Epson PC AX Technical Manual page 183

REV .A DIAGRAMS
AHn
REFERENCE MATERIALS
TABLE 7-2-4. GAATCB PIB DESCRIPTIOB
SYMBOL
1/0* PIB NO. NAKE AND FUBCTIOB
A23-17 Tri
SA19-17 O&H-Z
LA23-17 l
BHE
SBHE
XBHE
MIO
SHIO
IOWN
lORN
MEMHN
MEHRN
XIOWN
XlORN
XMWN
XMRN
SMWN
SHRN
DLA
GSAN
ALE
OEN
DXRW
GSRWN
RFMRN
RFCN
VI
VO
NDIl
NDI2
NDO
NDIl
I
Tri
Tri
I
O&H-Z
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
O&H-Z
O&H-Z
I
I
I
I
I
I
I
I
I
T
l
I
o
I
30,29,27,26,
24-22
45-47
21-18,15-13
7
9
11
8
10
53
52
50
51
38
36
35
34
43
44
2
1
3
4
55
54
5
6
63
62
57
58
56
60
CPU address bus.
System address bus. (8-bit connector).
Unlatched system address bus. (16-bit
connector).
CPU bus high enable signal.
System bus high enable signal. (16-bit
connector).
Internal bus high enable signal.
CPU memory / 1/0 signal.
Buffered memory / 1/0 signal.
System 1/0 write signal. (8-bit connector).
System 1/0 read signal. (8-bit connector).
System memory write signal (16-bit connector).
System memory read signal (16-bit connector).
Internal 1/0 write signal.
Internal 1/0 read signal.
Internal memory write signal.
Internal memory read signal.
System memory write signal (8-bit connector).
System memory read signal (8-bit connector).
Direction control of CPU address bus (A23-17)
buffer. When high, LA23-17 are driven by A23-
17. And when low A23-17 are driven by LA23-17.
Enable control of address bus (SAI9-17) buffer.
When low, SA19-17 are driven by AI9-17.
Address latch enable. A19-17 and MIO and BHE
are latched by ALE.
Enable control of latched address (A19-17), MIO
and BHE. When low, SA19-17 are driven by latched
A19-17. When low, SMIO and SBHE are driven by
latched MIO and BHE, respectively.
Direction control of CPU control bus. When
high, XIOWN, XIORN, XNWN and XNRN are driven by
IOWN, IORN, MEMWN, and HE}ffiN respectively. When
low, IOWN, TORN, MEMWN and MEMRN are driven by
XIOWN, XIORN, XMWN, and XHRN respectively.
Enable control of SMWN and SMRN. When
10\.,
SHWN
and SMRN are enabled.
Memory read pulse of refresh cycle. RFMRN is
used in conjunction with RFCN signal.
Refresh enable. When low, MEMRN, XMRN and SMRN
are driven by RFMRN.
Input of inverter.
Output of inverter.
Input of NAND gate.
Input of NAND gate.
Output of NAND gate.
Input of NOR gate.
7-9