Epson PC AX Technical Manual page 185

REV .A DIAGRAMS AHn REFERENCE MATERIALS
TADLE 7-2-6. GAA'IDB PIB DESCRIPTIOB
SYMBOL
D15-0
MD15-0
SD15-0
DD
GDHN
GDLN
CBA
SBA
DMD
GMDHN
GMDLN
D245
G245N
1/0*
Tri
Tri
Tri
I
I
I
I
I
I
I
I
I
I
PllI
!K).
63-60,31-28
4-1,33-36
59,56-54,43,
42,38,37,27,
24,23,22,11,
10,6,5
53-50,47-44
21-18,15-12
41
40
39
58
57
7
8
9
25
26
NAME AND FUBCTIOB
CPU data bus.
Memory data bus.
System data bus.
Direction control of CPU data bus(D15-0) buffer.
When low, CPU reads data from MD15-0 or SD15-0.
Enable control of CPU data bus high byte (D15-8)
buffer. When low,
it
enables high byte.
Enable control of CPU data bus low byte (D7-0)
buffer. When low,
it
enables low byte.
Read data latch. SD7-0 are latched at CBA rising
edge.
SBA selects latched or un-latched data. When
high, latched data are selected. SBA is used in
conjunction with CBA signal.
Direction control of Memory data bus (HD15-0)
buffer. When high Memory data is read.
Enable control of Hemory data high byte (MD15-8)
buffer. When low, it enables high byte. GMDEN
is used in conjunction with D~ID signal.
Enable control of Hemory data low byte (MD7-0)
buffer. When low, it enables low byte. GHDLN is
used in conjunction with DMD signal.
Direction control of low to high byte conversion
buffer. When low, it indicates high to low byte
conversion during data transfers to 8-bit
peripherals (write). When high, it indicates low
to high byte conversion during data transfers
from 8-bit peripherals (read).
Enable control of low to high byte conversion
buffer. It is active low signal and is used in
conjunction with D245 signal.
*
Legend: I
=
Input P in
o
=
Output P in
Tri Tri-state Pin (Input, Output, High-impedance)
7-11