I/O Channel - IBM 5150 Hardware Reference Manual

I/O Channel
The I/O channel is an extension of the 8088 microprocessor bus.
It is, however, demultiplexed, repowered, and enhanced by the addition
of interrupts and Direct Memory Access (DMA) functions.
The I/O channel contains an 8-bit bidirectional data bus, 20 address
~
lines, 6 levels of interrupt, control lines for memory and I/O read or
write, clock and timing lines, 3 channels ofDMA control lines, memory
refresh timing control lines, a channel check line, and power and ground
for the adapters. Four voltage levels are provided for I/O card
+
5 V dc, ­
5 V dc,
+
12 V dc, and -12 V dc. These functions are provided in a 62-pin
connector with 100 mil card tab spacing.
A ready line is available on the I/O channel to allow operation with
slow I/O or memory devices. If the channel's Ready line is not
activated by an addressed device, all processor generated memory
read and write cycles take four 210 ns clock or 840 ns/byte. All
processor-generated I/O read and write cycles require five 210 ns
clocks or 1.05 m sec/byte. All DMA transfers require five clocks for a
cycle time of 1.05 m sec/byte. Refresh cycles are present once every 72
clocks or approximately 15 m sec and require five clocks or approxi ­
mately 7% of the bus bandwidth.
I/O devices are addressed using I/O mapped address space. The ,,--......,
channel is designed so that 512 I/O device addresses are available to
the I/O channel cards.
A channel check line exists for reporting error conditions to the
processor. Activating this line results in a NMI to the 8088 processor.
Memory Expansion Options use this line to report parity errors.
The I/O channel is repowered so there is sufficient drive to power
all five System Expansion Slots, assuming two loads per slot. The
IBM Option I/O adapters typically use only one load. A graphic
illustration of the System I/O Channel and its descriptions are on the
following pages.
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