Technologic Systems TS-7400 Hardware & Software Installation page 44

Register Address
0x6000_0000
0x23C0_0000
0x2380_0000
0x2340_0000
0x2300_0000
0x2200_0000
0x1300_0000-0x1300_0003
0x1240_0001
0x1240_0000
0x12c0_0003
0x12c0_0002
0x12c0_0001
0x12c0_0000
0x1200_0001
0x1200_0000
© May, 2010
TS-7400/TS-9441 MANUAL
APPENDIX B: MEMORY AND REGISTER MAP
Function
bit 4:3 - reserved
bit 5 - flash busy signal
bit 7:6 - reserved
NAND flash data register
WDT Feed register (bits 0-2)
WDT Control register (bits 0-2)
TS-CPLD revision register
bit 2:0 - CPLD revision number
bit 7:3 - reserved
SPI EEPROM chipselect control
bit 0 - reserved
bit 1 - onboard SPI EEPROM chip-select enable
bit 2 - offboard (boot hijacker) SPI EEPROM chip-
select
bit 7:3 - reserved
Model Number (bits 0-2)
SD card controller (/dev/sdcard0/disc0 in Linux)
UART #2 (/dev/ttyTS0 in Linux) DAT register
UART #2 (/dev/ttyTS0 in Linux) STAT register
bit 0 - TBRE, Transmit buffer empty (RO)
bit 1 - DR, Receive data ready (RO)
bit 2 - OERR, Overflow error (RO)
bit 4:3 - reserved
bit 7:5 - MODE, baud rate (RW)
0 - 115200 8N1
1 - 57600 8N1
2 - 38400 8N1
3 - 19200 8N1
4 - 9600 8N1
5 - 4800 8N1
6 - 2400 8N1
7 - UART off, IRQ disabled
GPIO data register for DIO_8 to DIO_15
GPIO data register for DIO_0 to DIO_7/GPBUS
address register
GPIO direction for DIO_8 to DIO_15 ('1' means
output)
GPIO direction for DIO_0 to DIO_7 ('1' means output)
GPIO direction/data for DIO_16 to DIO_19
bit 3:0 - data register
bit 7:4 - data direction register ('1' means 'output')
TS-7400 control register
bit 0 - if set, enables UART #0 on DIO_18 and
DIO_19 pins
bit 1 - if set, enables IRQ on DIO_11 pin
bit 2 - if set, enables DRQ on DIO_12 pin
bit 3 - if set, enables 14.7456Mhz clock on DIO_13
pin
bit 7:4 - reserved
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