General Purpose 8-Bit Multiplexed Bus (Gpbus) - Technologic Systems TS-7400 Hardware & Software Installation

5.4 General Purpose 8-bit Multiplexed Bus (GPBUS):

To use the general purpose bus, GPIO pins 7-0 first MUST be programmed as general
purpose outputs by writing an 0xff to 0x12c0_0000. Also, GPIO pins 8-10 must also be
programmed as outputs if all 3 strobes will be used (ALE, RD, and WR). A strobe pin set
up as a GPIO input will not be toggled at the appropriate times during a GPBUS bus
cycle-- this can save GPIO pins in the case of a read-only or write-only bus, but is
probably not what you want. GPIO #8 is the ALE, #9 is RD, and #10 is WR. The typical
usage of ALE is an active high signal representing the period of time during which the
address/data bus is driving the address. The read and write strobes are typically active
low and signified as RD# and WR#. The polarity of each strobe is programmed by the
contents of the GPIO data register for pins 8, 9, and 10. Knowing the data register bit
locations of ALE, RD, and WR, you should then program them to default output ALE
asserted with RD and WR deasserted. In the case of ALE active high, WR/RD active low,
the value written to bits 2-0 at 0x12c0_0003 should be 7 (binary 111). For the purposes
of the timing diagrams below, we will assume this configuration.
The default timing of the GPBUS cycle uses a 55 nS read/write pulse when
reading/writing the data register at 0x60c0_0000. This is with the EP9302 bus cycles
programmed for 60nS operation. (EP93xx SMCBCR6 register value 0x34c2). Although
you may not change this value since the NAND flash chip is on the same EP93xx chip
select, you may change the SMCBCR7 register for slower or faster operation and use the
data register alias at 0x70c0_0000. The GPBUS waveform for 0x60c0_0000 accesses
looks like this:
___________________________________________
RD#
_________ _ _ _ _ _ _ _ _ _________________
WR#
__
ALE \____________________________/
_________
AD ___addr__XXXX_______data_______XX___addr___
|-#1--|
#1 - address hold - 13nS
#2 - address to data transition time - 6nS
#3 - RD# or WR# pulse - 55nS
#4 - data hold, RD#/WR# deassert to ALE assert - 6nS
The above timing should be compatible with a standard 74HC373 octal latch chip should
you wish to de-multiplex the address/data bus into something more similar to ISA/PC104
externally. If you have questions about whether a particular design will work or not,
please feel free to contact Technologic Systems with your schematic for review.
© May, 2010
COMMON INTERFACES GENERAL INFORMATION
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