Signal Processing Latency - Lake LM Series Operation Manual

Digital audio processors

Hide thumbs Also See for Lake LM Series:

Quick start manual (30 pages)

Table Of Contents

Table of Contents

When using automatic detection, the AES3 digital input is monitored and will switch the clock source back

and forth depending on the availability of an AES3 signal.

Please refer to the Lake Controller Operation Manual for additional information.

9.4.3

Dante Clock Configuration

Dante uses its own digital clocking technology across the Ethernet network to ensure that all Dante devices

are synchronized. As part of this logic, an order of priority is defined to identify which device becomes the

Dante Master. A Dante-capable device set as Preferred Clock Master is chosen as the highest priority,

followed by a device with a valid AES3 signal, then an internally generated clock.

Dante only operates at 48 kHz or 96 kHz, and therefore only uses the Primary Digital Clock to lock the

sample rate for the Dante Master. The Primary Clock on all Dante Slaves will be overridden by the Dante

Clock. If an additional digital input signal is required on a device that is already a Dante slave, this secondary

digital input must be locked using the SRC clock.

The front panel I/O Status View indicates if that device is selected as Dante Clock Master. Confirmation of

Dante Master / Slave status is also displayed in the Lake Controller. The Dante Preferred Master setting can

be set from the Lake Controller I/O Configuration screen, or via the Dante Controller.

For further information on Digital Clock configuration

and the Lake Controller user interface, please refer

to the Lake Controller Operation Manual.

9.5