Lake LM Series Operation Manual page 65

Application Guide
In Figure 9-1, each circled C represents a choice point. A choice point is a user‐interface control that can
be configured using the Lake Controller software. Please refer to the Lake Controller Operation Manual for
further information.
Figure 9-1 indicates internally generated clocks with
base-rate multiples of 44.1 kHz or 48 kHz. This
should not be confused with the internal DSP
sample rate of 96 kHz.
Both the Primary and Sample Rate Converter (SRC) clocks can either generate their own internal clock
signal, or synchronize to an incoming AES3 signal. An incoming AES3 signal can be locked using automatic
clock detection or manual clock selection.
The Primary and SRC clocks produce multiple audio clocks derived from a base sample rate. The Primary
Clock's base rate is 48 kHz, which also derives the 96 and 192 kHz clocks. The SRC Clock's base rate can
be either 44.1 or 48 kHz. If the SRC Clock's base rate is 44.1 kHz, then 88.2 and 176.4 kHz clocks are also
derived; if the SRC Clock's base rate is 48 kHz, then 96 and 192 kHz clocks are also derived.
In most typical applications, SRC Clock will be set at a base rate of 44.1 kHz. A base rate of 48 kHz is
provided to allow for both synchronous (via Primary Clock) and asynchronous (via SRC Clock) I/O.
All clocks derived from the Primary and SRC clocks are available to drive the AES3 audio outputs. The
desired sample rate can be selected independently for each AES3 output pair, as shown on the right side of
Figure 9-1.
For example, you could configure AES1, AES2, and AES3 to provide 96 kHz AES3 outputs to drive digital
amplifiers in the sound system, and configure AES4 to provide a 44.1 kHz audio recording output for media
or broadcast purposes.
9.4.2 Clock Source Priorities
There are two options for clock source configuration: Manual Configuration or Automatic Detection.
For Manual Configuration, the selected internal or external clock source remains fixed regardless of whether
a compatible clock signal is preset.
For Automatic Detection, the most appropriate clock matching the selected base-rate is automatically
selected according to the following priorities.
1. AES1 (Input 1+2)
2. AES2 (Input 3+4)
3. AES3 (Input 5+6) - LM 44 Only
4. AES4 (Input 7+8) - LM 44 Only
5. Internal Clock
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Lake LM Series Operation Manual Rev 1.3.5