Hitachi SJ100DN DeviceNet Series Instruction Manual page 68

The control bits (Byte 0) of each host output instance use some or all of the bits defined
in the following table.
Bit Name
0 FW Run
1 RV Run
2 Fault Reset
3 Free Run Stop
4 —
5 Network Control
6 Network Reference
7 —
Host Input Instance Configurations – The following tables list the three configura-
tions for host input data (settable by P_47).
Inverter Produced Data, (Host) Input Instance (P_47) = 70
Byte Bit 7 Bit 6
0 —
1
2
3
The table below expands Byte 0 in the preceding table.
Bit Name
0 Trip
1 —
2 FW Run
3, 4, 5, —
6, 7
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Inverter Consumed Data, Control Byte
Bit = 0
Stop
Stop
—
—
—
Run/Stop control is local to
inverter
Output freq. / accel / decel is
from F_01, F_02, F_03
—
Bit 5 Bit 4
— — —
Inverter status (see status code table, next page)
Output frequency monitor (low byte), D_01 value
Output frequency monitor (high byte), D_01 value
Inverter Produced Data, Status Byte
Bit = 0
No faults exist
—
Inverter stopped or in RV
—
SJ100DN Inverter
Bit = 1
FW Run command
RV Run command
Reset the inverter, clear trip
Cause motor to free run
(coast) and stop
—
Run/Stop control is from
network host polled I/O
Output freq. / accel / decel is
from network host polled I/O
—
Bit 3 Bit 2 Bit 1
— FW Run —
Bit = 1
Trip exists, not cleared
—
Inverter in FW Run
—
67
Bit 0
Trip