Panasonic KX-P7100 Service Manual page 53

4.4.2. GDI ASIC ( IC3 )
1) CPU Interface
The CPU interface consists of an 8-bit data bus and control signals between GDI ASIC and CPU.
2) DRAM I/F
This block controls DRAM, which is the buffer where transient print data is stored.
3) KME ASIC I/F
This block is the interface with the KME ASIC ( IC6 ).
It receives the compressed print data through KME ASIC via Parallel I/F or USB I/F from host PC.
It decompresses the received print data, converts it into actual bit map data, and sends it to the engine as video data through the Engine
Interface. At this time, DRAM is transiently used as a buffer.
4) Engine I/F
Refer to 4.4.17.
53
KX-P7100