ASROCK Fatal1ty X99 Professional Series User Manual page 100

RAS to RAS Delay (tRRD_L)
The number of clocks between two rows activated in different banks of the same
rank.
Write to Read Delay (tWTR)
The number of clocks between the last valid write operation and the next read
command to the same internal bank.
Write to Read Delay (tWTR_L)
The number of clocks between the last valid write operation and the next read command to
the same internal bank.
Read to Precharge (tRTP)
The number of clocks that are inserted between a read command to a row pre-
charge command to the same rank.
Four Activate Window (tFAW)
The time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL)
Configure CAS Write Latency.
Third Timing
tREFI
Configure refresh cycles at an average periodic interval.
tCKE
Configure the period of time the DDR4 initiates a minimum of one refresh
command internally once it enters Self-Refresh mode.
tCCCD
Configure back to back CAS to CAS (i.e. READ to RAED or WRITE to WRITE)
from same rank separation parameter.
tCCCD_L
Configure back to back CAS to CAS (i.e. READ to RAED or WRITE to WRITE)
from same rank separation parameter.
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