Acer PD721 Service Manual page 16

CONFIG/
SEQUENCE
PROM
DPF2A CONTROL
VOLTAGE ENABLES
BIAS BIN
FPGA CLK
BIAS/RESET CONTROL
DMD CONTROL
VSYNCZ
MENORY CONTROL A
HSYNCZ
CONTROL
ACTDATA MENORY ADDRESS A(12)
MENORY ADDRESS A(12)
FPGA
TFIELD
MENORY ADDRESS B(12)
OLACT
MENORY CONTROL B
SYNCVAL
DMD CONTROL
LAMP CONTROL&STATUS
CWRSTZ
COLOR WHEEL INDEX
VSYNCZ, RESETZ
FLASH
PROGRAMMING
HEADER
IIC BUS MICRO
CONTROLLER
HITACHI
DOWNLOAD
HEADER
CLKIN
COLOR
WHEEL
CONTROL
COLOR WHEEL STATUS
+5V +12V
VCC2,VOFFSET,VBIAS
VERSET GENERATION
CLOCK
OSC
INPUTCLK
PBUS2
ALLEGRO
MOTOR
CONTROL
COLOR
WHEEL
DRIVE
VCC2 (DMD)
VCC2 (ASIC)
VOFFSET
VBIAS
VRESET
RESET ASIC
FPGA CLK
DATAPATH
DMD CLK
FORMATTER
DPF2A
SDRAM CLK
DMD DATA(0..63)
SDRAM A
SDRAM B
MBIASRST (16)
DMD
0.7" XGA
DATA(0..63)