Advanced Chipset Features; Dram Timing Selectable; Cas Latency Time - Intel M 910GML User Manual

BIOS SETUP

Advanced Chipset Features

This Setup menu controls the configuration of the chipset.

DRAM Timing Selectable

CAS Latency Time

DRAM RAS# to CAS# Delay
DRAM RAS# Precharge
Precharge delay (tRAS)
System Memory Frequency
SLP_S4# Assertion Width
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole at 15M-16M
PCI Express Root Port Func
** VGA Setting **
PEG/On Chip VGA Control
On-Chip Frame Buffer Size
DVMT Mode
DVMT/FIXED memory Size
SDVO Device Setting
SDVO LVDS Protocol
SDVO Panel Number
Boot Display
Panel Scaling
TV Standard
Video Connector
TV Format
Onboard PCI-E LAN
LAN PXE Option ROM
DRAM Timing Selectable
This option refers to the method by which the DRAM timing is selected.
The default is By SPD.
CAS Latency Time
You can configure CAS latency time in HCLKs as 3 or 4 or 5. The
system board designer should set the values in this field, depending on
the DRAM installed. Do not change the values in this field unless you
change specifications of the installed DRAM or the installed CPU.
DRAM RAS# to CAS# Delay
This option allows you to insert a delay between the RAS (Row Address
Strobe) and CAS (Column Address Strobe) signals. This delay occurs
when the SDRAM is written to, read from or refreshed. Reducing the
delay improves the performance of the SDRAM.
30
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
By SPD
3
3
3
9
400MHZ
1 to 2 Sec
Enabled
Ensabled
Disabled
Press Enter
Auto
8MB
DVMT
128MB
LVDS + DVI
1CH SPGW, 24bit
1024x768
CRT+DVI
Auto
Off
Automatic
Auto
Enable
All Disable
MI920 User's Manual
ITEM HELP
Menu Level >