Yamaha DSP-E800 Service Manual page 29

IC5 : IS61C1024-20J (1M SRAM)
131072-word x 8-bit High Speed Static RAM
1
NC
A3 2
A4 3
4
A5
A6 5
A7 6
7
A8
TOP VIEW
A9 8
A10 9
10
A11
A12 11
12
A13
13
D1
D2 14
15
D3
GND 16
NOTE)
A0-A16:
D1-D8:
/CE1,CE2: Chip enable input 1,2
/OE:
/WE:
IC7 : AK4324-VF-E2 (DAC)
1-bit D/A Converter
1
DVSS
DVDD 2
CKS 3
4
MCLK
/PD 5
BICK 6
TOP VIEW
7
SDATA
LRCK 8
9
SMUTE
10
DFS
DEM0 11
12
DEM1
Pin Pin
I/O Function
No. Name
1 DVSS Ground (digital)
2 DVDD Power supply (digital)
3 CKS I Master clock (MCLK) select input (Fixed L)
Normal speed (L:256fs, H:384fs)
High speed (L:128fs, H:192fs)
4 MCLK I 256fs bit clock input from DIR5
5 /PD I Power-down and reset, initial clear input from
AC3D2av (L:Reset)
6 BICK I 64fs bit clock input from DIR5
7 SDATA I Serial data input from AC3D2av
8 LRCK I 1fs word clock input from DIR5
9 SMUTE I Soft mute detect input (H:Soft mute, L:off)
10 DFS I Double speed sampling mode select input from
DIR5 (L:Normal speed, H:High speed)
32
VCC
27,28
31 A2
31,
30 CE2 A0-A16
2-12,
23,25
29
/WE
26
28 A1
27 A0
13-15,
26
A16
D1-D8
17-21
25 A15
24 /OE
23
A14 /CE1
22 /CE1 CE2
/WE
21
D8
20
D7 /OE
19 D6
18
D5
17 D4
Address input
Data input/output
Output enable input
Write enable input
24 DZFL
23 DZFR
LRCK
BICK
22 AVDD
SDATA
21 VREF
20 AVSS
/PD
19 AOUTL+
SMUTE
18 AOUTL-
17 AOUTR+
DFS
16 AOUTR-
15
DIF2
14 DIF1
13 DIF0
DECODER
(512-row x 2048-column)
I/O DATA
CONTROL
22
30
CONTROL
CIRCUIT
29
24
Mode /WE /CE1 /CE2 /OE
Not Selected X H X X
(Power-down)
X X L X
Output Disabled
H L H H
Read
H L H L
Write L L H X
NOTE) H: High Level L: Low level
DIF0 DIF1 DIF2 DEM0 DEM1
13 14 15 11 12
8
SERIAL INPUT DE-EMPHASIS
6
INTERFACE CONTROL
7
∆ ∑
8x
5
INTERPOLATOR MODULATOR
9
∆ ∑
8x
INTERPOLATOR MODULATOR
10
CLOCK
DIVIDER
4 3 2 1
MCLK CKS DVDD DVSS
Pin Pin
I/O
No. Name
11 DEM0 I De-emphasis frequency select input 0 (Fixed H)
12 DEM1 I De-emphasis frequency select input 1 (Fixed L)
13 DIF0 I Digital input format input 0 (Fixed L)
14 DIF1 I Digital input format input 1 (Fixed H)
15 DIF2 I Digital input format input 2 (Fixed L)
16 AOUTR- O Rch negative analog output
17 AOUTR+ O Rch positive analog output
18 AOUTL- O Lch negative analog output
19 AOUTL+ O Lch positive analog output
20 AVSS Ground (analog)
21 VREF I Reference voltage input
22 AVDD Power supply (analog)
23 DZFR O Rch zero input detect output
24 DZFL O Lch zero input detect output
DSP-E800
131072-word x 8-bit
MEMORY ARRAY
COLUMN I/O
32 VCC
16 GND
Data I/O Power
High impedance Standby
High impedance On
High impedance On
Output On
Input On
X: Don't care
AVDD AVSS
22 20
24 DZFL
19
AOUTL+
SCF
18 AOUTL-
17 AOUTR+
SCF
16 AOUTR-
23 DZFR
21
VREF
Function
26