Pin Descriptions; Sda5275; Features - Toshiba 29VH27E Service Manual

• Schmitt trigger filtered inputs for noise suppression
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to eight devices may be connected to the same bus for up to 256K bits total memory
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC packages
• Temperature ranges
• Commercial (C): 0°C to +75°C
• Industrial (I): -40°C to +85°C

14.3.3.Pin Descriptions

A0, A1, A2 Chip Address Inputs
The A0..A2 inputs are used by the 24LC32A for multiple device operation and conform to the 2-wire bus
standard. The levels applied to these pins define the address block occupied by the device in the
address map. A particular device is selected by transmitting the corresponding bits (A2, A1, A0) in the
control byte.
SDA Serial Address/Data Input/Output
This is a Bi-directional pin used to transfer addresses and data into and data out of the device. It is an
open drain terminal, therefore the SDA bus requires a pull up resistor to V
2 kO for 400 kHz) For normal data transfer SDA is allowed to change only during SCL low. Changes
during SCL HIGH are reserved for indicating the START and STOP conditions.
SCL Serial Clock
This input is used to synchronize the data transfer from and to the device.
WP
This pin must be connected to either V
(read/write the entire memory 000-FFF). If tied to V
memory will be write-protected. Read operations are not affected.
W
CC
+2.5V to 6V Power Supply
W
SS
Ground

14.4.SDA5275

14.4.1.Features

• Single chip teletext IC
• Analog CVBS-input with onchip clamping circuitry
• Slicer
• Supports level 1, 2.5 and 3.5 ETSI teletext standard
• Stores up to 14 teletext pages on chip
• Stores up to 2048 teletext pages with external 16 M memory
• SDA 5275: full level 2.5 processing
• Analog RGB-output
• 41 Latin script languages
• 12 ´ 10 character size
• Parallel display attributes
• 64 from 4096 colors selectable
• Enhanced flash modes
• Dynamically redefinable character set (DRCS, PCS)
• Pixel graphics
• Full screen display (64 ´ 32 or 80 ´ 24 character positions)
• Horizontal and vertical scrolling
• Graphic cursors
• 4:3 and 16:9 display
• Multinorm display (50/60/100/120 Hz)
• RISC-processor
• Firmware downloadable
2
• I C / 3 wire UART-interface (1 Mbit/s)
• Independent clocks for acquisition and display
or V . If tied to V
SS CC
, WRITE operations are inhibited. The entire
CC
7
(typical 10 kO for 100 kHz,
CC
, normal memory operation is enabled
SS