WEISS Vesta Owner's Manual page 8

OWNERS MANUAL FOR WEISS VESTA FIREWIRE INTERFACE
Jitter handling in the VESTA in more detail
The Jitter Elimination Technologies (JET) PLL on the chip used in the VESTA feature state-of-the art
jitter rejection abilities and extremely low intrinsic jitter levels. Like all phase-locked loops, JET PLL
use feedback to lock an oscillator to a timing reference. They track slow reference changes, but
effectively free-run through rapid modulations of the reference (i.e. flywheel like). From a jitter
transfer point of view, they provide increasing jitter attenuation above some chosen corner
frequency.
Jitter attenuation is just one aspect of PLL design. Other considerations include frequency range
and intrinsic jitter. It can be shown that conventional designs are bound by a fundamental tradeoff
between these three aspects. For example, specifying a frequency range of one octave means using
a low-Q oscillator. But that makes for high intrinsic jitter when the loop corner frequency is held
down. Conversely, good jitter attenuation and low intrinsic jitter can be had by using a voltage-
controlled crystal oscillator (VCXO). But the frequency range is then tiny. A further consideration is
that only low-Q oscillators are easy to integrate on chip. JET PLL sidestep the above-mentioned
tradeoff. It incorporates two loops. One is largely or wholly numeric, and has its corner frequency
set low enough to give good reference-jitter attenuation. The other regulates the analog oscillator
and has its corner frequency set much higher, to moderate the intrinsic jitter. The two corner
frequencies might be around 10 Hz and 100 kHz, for example. Another benefit of having a high
corner frequency in the analog loop is that interference, e.g. via the oscillator's supply rail, is more-
effectively suppressed. JET PLL requires a fast, stable, fixed-frequency clock. It is this that gives it
stability in the band between the two corner frequencies. (Equally, in this band any jitter on this
clock passes straight through to the JET PLL's clock output.) The stable clock is usually derived
from a free-running crystal oscillator. JET PLL contains a number-controlled oscillator, which can
also be called a fractional frequency divider. Like the analog oscillator, this injects jitter. Typically,
spectrum shaping is used to push most of that jitter up to frequencies where it will be heavily
attenuated by the analog loop. As well as frequency-locking the analog oscillator to the provided
reference, JET PLL can also phase-lock an associated frame sync to the reference.
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Page: Date: 10/08 /dw